||Duo to the fast growth of leakage power dissipation,|
power-gating technique is a often used to reduce leakage
power and dynamic power simultaneously. While designing a
power gating design, two critical issues are often
discussed: sleep transistor sizing and wakeup scheduling.
However, solving the two critical issues requires the same
essential information, the supply current waveform of the
main circuits. Most existing approaches assume that the
current information of the main circuits can be obtained
from transistor-level simulation. Although this approach can
obtain highly accurate current waveforms, it often requires
heavy simulation overhead. Until now, not too many
researches focus on studying a fast and efficient current
model for power gating designs to analyze the wake-up
current impacts. Therefore, a gate-level current model is
proposed using standard cell library format to estimate the
wake-up current. According to the input values of each cell,
the proposed method will choose an existing switching
current waveform and modify it to build the wake-up current
model. Thus, the wake-up current waveform can be obtained by
the proposed approach without extra characterization, except
the input values and the equivalent resistance and
capacitance of the power gate. The experimental results show
that the proposed gate-level wake-up current model can
provide accurate enough current waveform to help designer
analyze the rush current effects at early design stages.
|| Power consumption for various technologies. [Online].|
 K. Michael, F. David, A. Rob, G. Alan and K. Shi, ”Low
Power Methodology Manual For System-on-Chip Design”,
 K. Shi, Z. Lin, Y.-M. Jiang and Y. Lin, “Simultaneous
Sleep Transistor Insertion and Power Network Synthesis for
Industrial Power Gating Designs”, ACADEMY PUBLISHER, Journal
of Computer, Vol 3. No 3. March 2008.
 Z. Liu and V. Kursun, “Characterization of wake-up
delay versus sleep mode power consumption and sleep/active
mode transition energy overhead tradeoffs in MTCMOS
circuits”, the 51st Midwest Symposium on Circuits and
 K. Shi, Z. Lin and Y.-M. Jiang, ”A Power Network
Synthesis Method for Industrial Power Gating Designs”,
International Symposium on Quality Electronic Design, 2007.
 D. Howard and Kaijian Shi, “Power-On Current Control In
Sleep Transistor Implementations”, International Symposium
on VLSI Design Automation and Test, 2006
 A. Sagahyroon and F. Aloul, “Maximum Power-Up Current
Estimation in Combinational CMOS Circuits”, Mediterranean
Electrotechnical Conference, 2006.
 A. Todri, S.-C. Chang and M. Marek-Sadowska,
“Electromigration and Voltage Drop Aware Power Grid
Optimization for Power Gated ICs”, International Symposium
on Low Power Electronics and Design, 2007.
 F. Li, L. He, J.M. Basile, R.J. Patel and H.
Ramamurthy, ”High-level area and power-up current estimation
considering rich cell library”, Asia and South Pacific
Design Automation Conference, 2004.
 F. Li, L. He and K.K. Saluja, ”Estimation of maximum
power-up current”, Asia and South Pacific Design Automation
 Y.-F. Tsai, D. Duarte, N. Vijaykrishnan and M. J.
Irwin, “Implications of Technology Scaling on Leakage
Reduction Techniques”, Design Automation Conference, 2003.
 A. Ramalingam, B. Zhang, D.Z. Pan and A. Devgan,
“Sleep Transistor Sizing Using Timing Criticality and
Temporal Currents”, Asia and South Pacific Design Automation
 H. Jiang and M. Marek-Sadowska, “Power gating
scheduling for power/ground noise reduction”, Asia South
Pacific Design Automation Conference, 2005.
 C. Long and L. He, “Distributed sleep transistor
network for power reduction”, Design Automation Conference,
 Library Compiler User Guide: Modeling timing and power
technology libraries, Synopsys, March 2003.
 M.S. Lee and C.H. Lin, C.N. Liu, “Dynamic Supply
Current Waveform Estimation with Standard Library
Information”, IEICE TRANS. FUNDAMENTALS, VOL.E93-A, NO.3
pp.595-606, March 2010.
 Mu-Shun Matt Lee, Kuo-Sheng Lai, Chia-Ling Hsu and
Chien-Nan Jimmy Liu, "Dynamic IR Drop Estimation at Gate
Level with Standard Library Information", IEEE International
Symposium on Circuit and Systems (EI), pp. 2606-2609, May