博碩士論文 975201052 詳細資訊




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姓名 何偉誌(Wei-Zhi He)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 砷化銦/銻化鋁高電子遷移率場效電晶體之鈍化製程發展與元件特性研究
(Passivation Process Development and Device Characterization for InAs/AlSb High Electron Mobility Transistors)
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摘要(中) 本論文為利用砷化銦材料優異的高電子遷移率及優異電子飽和速度特性,發展低功率和高速的異質接面場效電晶體(HFET)。由於銻化物材料系統的化學穩定性並不好,在元件製作時容易引起磊晶材料衰化,因此我們將藉著改善磊晶材料的品質和發展鈍化製程,防止元件電性的衰化,最佳化其直流及高頻特性。
我們利用快速熱退火製程將歐姆接觸電阻降低至RC=0.06Ω-mm。閘極長度2μm的元件特性於汲極偏壓VDS=0.4V下,其汲極飽和電流為IDSS=650mA/mm及轉導增益為gm=1,223mS/mm,電流增益截止頻率與閘極長度乘積比高達fT×Lg=68GHz-μm。另外利用鈍化製程降低缺陷能態密度,在脈波電流-電壓量測分析中,以一階段鈍化元件的表面缺陷最不顯著,且具有低閘極漏電流特性和改善次臨限行為的Ion/Ioff =3831和S.S.=111mV/dec,元件的良率從5%提升至95%。最後,我們利用一階段鈍化製程,製作0.5μm的T型閘極元件,證明fT=93GHz和fmax=82GHz之高頻性能。
摘要(英) This thesis develops low-power and high-speed heterpjunction field-effect transistors using InAs channels which have very high electron mobility and excellent peak velocity. Due to chemical instability of lattice-matched antimonides which easily degrade epitaxial materials, improvements of epitaxial quality and developments of passivation processes are performed to alleviate its effects on dc and rf performances.
Ohmic contacts are reduced as low as 0.06Ω-mm utilizing a rapid thermal annealing process. In a 2μm-gate-length device, drain current is 650mA/mm and transcondutance is 1,223mS/mm at VDS=0.4V. A product of cut-off frequency and gate length as high as 68 GHz-μm is achieved. In addition, an optimized passivation process is successfully developed to decrease trap density. In a pulsed I-V measurement, the charge trapping in a one-step passivated device is least pronounced and improved subthreshold characteristics of Ion/Ioff =3831 and S.S.=111mV/dec are demonstrated. Device yield is raised from 5% to 95%. Finally, a HEMT of a 0.5μm e-beaming writing T-gate shows excellent rf performance of fT=93GHz and fmax=82GHz using the developed one-step passivation approach.
關鍵字(中) ★ 鈍化製程
★ 砷化銦
★ 高電子遷移率
關鍵字(英) ★ high electron mobility
★ HFET
★ HEMT
★ InAs/AlSb
★ passivation
論文目次 摘要 I
Abstract IV
謝誌 V
目錄 VI
圖目錄 X
表目錄 XVI
第一章 導論 1
1-1 砷化銦/銻化鋁之高速電子遷移率電晶體發展現況 1
1-2 掘入式閘極元件之發展現況 9
1-3 鈍化製程元件之發展 12
1-4 論文架構 15
第二章 磊晶結構設計與製程發展 16
2-1 前言 16
2-2 磊晶結構設計與材料分析 16
2.2.1 砷化銦/砷化銦鋁(InAs/InAlAs)保護層磊晶結構 16
2.2.2 雙層保護層(double cap)磊晶結構 19
2-3 歐姆接觸電阻之發展 24
2.3.1 無摻雜砷化銦/砷化銦鋁磊晶結構 24
2.3.2 高摻雜砷化銦/砷化銦鋁磊晶結構 26
2.3.3高摻雜砷化銦鎵/砷化銦鋁磊晶結構 28
2-4 標準製程發展 29
2-5 鈍化層製程之發展 30
2.5.1 二階段鈍化層製程之發展 31
2.5.2 閘極後鈍化層製程之發展 33
2-6 電子束微影T型閘極元件製程之發展 34
2.6.1 次微米T型閘極製程的發展 34
2.6.2 次微米T型閘極元件製作 36
2-7 結論 37
第三章 砷化銦/銻化鋁HFET之元件特性 38
3-1 前言 38
3-2 標準元件性能 38
3.2.1 砷化銦保護層元件 38
3.2.2 砷化銦鋁保護層元件 45
3-3 鈍化層發展元件性能 48
3.3.1一階段鈍化層之元件 48
3.3.2兩階段鈍化層之元件 51
3.3.3 閘極後鈍化製程之元件 54
3-4 掘入式閘極元件 59
3.4.1 高摻雜砷化銦元件 59
3.4.2 高摻雜砷化銦鎵元件 62
3-5 高性能小線寬元件 66
3.5.1 小線寬標準元件 66
3-6 結論 68
第四章 討論 70
4-1 前言 70
4-2 元件特性的改善 70
4.2.2 捕捉缺陷能態對元件性能之影響 75
4.2.3 隨時間增加之元件特性變化 79
4-3 鈍化製程元件性能之討論 82
4.3.1 元件直流性能比較 82
4.3.2 鈍化元件之捕捉缺陷能態的分析 87
4.3.3 鈍化層對於衝擊離化之影響 92
4-4 結論 96
第五章 結論與未來發展 97
參考文獻 100
附錄 104
附錄1 標準製程 104
附錄2 閘極後鈍化製程 108
附錄3 製程前鈍化製程 112
附錄4 掘入式閘極製程 117
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指導教授 林恒光(Heng-Kuang Lin) 審核日期 2010-8-10
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