矽基板雜訊耦合與防護環設計分析

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姓名

顏志佑(Chih-yu Yen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

矽基板雜訊耦合與防護環設計分析
(Si Substrate Noise Coupling and Guard Ring Analysis)

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摘要(中)

隨著科技的進步，積體電路的微小化，將數位與類比電路整合在同一晶片上是一個未來的趨勢，但類比電路會受到數位電路所產生的基板雜訊的影響而改變其特性，因此基板雜訊在積體電路設計是一個不可忽視的議題。
本論文主要研究內容分為兩部分，第一部分為利用TSMC 0.18 μm CMOS製程設計一普遍應用於元件設計中，抑制雜訊的結構防護環，並觀察其在不同偏壓以及在低頻和高頻時的隔離度，並歸納出不同條件時的抑制能力。
第二部分為基板雜訊對射頻電路耦合效應，由訊號產生器將不同頻率、振幅之方波訊號灌入到基板中，觀察雜訊對一操作頻率為21 GHz之電壓控制振盪器的輸出功率和相位雜訊的變化，當輸入的方波振幅和頻率越大，電路所受到的影響越大。在得知電路所受到的影響後，進一步的則是將防護環圍繞整個電路來抑制基板雜訊，並給予防護環適當的偏壓改變其抑制能力。

摘要(英)

Continuous scaling of CMOS technology has resulted in chips with digital and analog circuit integrating on the same chip. However, the performance of the analog circuits will degrade due to substrate noise generated by the digital circuits. Substrate noise is an effect that can no longer be ignored in integrated circuit design.
This research content divides into two parts. First we proposed a novel structure as guard ring for device to suppress substrate noise by tsmc 0.18 μm CMOS technology. We applied bias to the guard ring and observed the isolation for low and high frequency. Finally we concluded the best condition for the isolation.
The second part is substrate noise coupling effect to circuit. The effect of signal on the VCO was investigated by applied various magnitudes and frequency square signal to the substrate in term of output power and phase noise. The output power and phase noise was degraded for various magnitudes and clock frequencies of the square signal applied. Further, the suppression of the signal on the VCO by the global guard ring was demonstrated and compared for various guard ring bias schemes.

關鍵字(中)

★ 基板雜訊
★ 防護環

關鍵字(英)

★ substrate noise
★ guard ring

論文目次

摘要 I
Abstract II
目錄 III
圖目錄 V
表目錄 VIII
第一章緒論 1
1.1研究背景與動機 1
1.2相關研究發展 4
1.3論文架構 5
第二章何謂基板雜訊及其傳輸機制 6
2.1簡介 6
2.2何謂基板雜訊及其來源 6
2.3基板雜訊耦合機制 9
2.3.1基板雜訊傳輸機制 9
2.3.2基板雜訊接收機制 10
2.4抑制基板雜訊方法與文獻回顧 11
第三章基板雜訊防護環設計與量測分析 14
3.1簡介 14
3.2防護環設計與Medici模擬結果 14
3.2.1防護環設計 14
3.3防護環實際製作與量測結果 23
3.3.1防護環實際製作 23
3.3.2防護環量測結果 25
3.4基板雜訊耦合分析 31
3.5等效電路 34
3.6 結論 37
第四章基板雜訊對射頻電壓控制振盪器之耦合影響 38
4.1 簡介 38
4.2 電壓控制振盪器架構 39
4.3 基板雜訊耦合影響測量與分析 40
4.3.1電路佈局圖 40
4.4 利用防護環抑制基板雜訊之量測結果 49
4.4.1電路佈局圖 49
4.5 結論 55
第五章結論 56
參考文獻 57
附錄 A 60
附錄 B 65

參考文獻

[1] N. Checka, D. D. Wentzloff, A. Chandrakasan, R. Reif, ”The Effect of Substrate Noise
on VCO Performance,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2005,pp.
523 – 526.
[2] M. A. Méndez, D. Mateo, X. Aragonès, J. L. González, ”Phase noise degradation of
LC-tank VCOs due to substrate noise and package coupling,” in Proc. Conf. Solid-State
Circuits, 2005, pp. 105 – 108.
[3] S. Magierowski, K. Iniewski, C. Siu, “Substrate Noise Coupling Effect
Characterization for RF CMOS LC VCOs,” in Proc. 3th IEEE NEWCAS Conf., 2005,
pp.199 - 202
[4] C. Andrei, O. Valorge, F. Calmon, J. Verdier, C. Gontrand, ”Impact of substrate
perturbation on a 5GHz VCO spectrum,” in Proc. 16th Int.Microelectronics Conf. , 2004, pp.684-687.
[5] S. Bronckers, G. Vandersteen, L. D. Locht, M. Libois, G. V.Plas, Y. Rolain, ”
Experimental Analysis of the Coupling Mechanisms Between a 4 GHz PPA and a 5–7 GHz LC-VCO,” IEEE Transactions on Instrumentation and Measurement, vol. 58, no. 8, pp. 2706-2713, 2009.
[6] E. Charbon, R. Gharpurey, P. Miliozzi, R. G. Meyer, A. S. Vincentelli, Substrate noise：
analysis and optimization for IC design, Norwell, Massachusetts, Kluwer Academic
Publishers, 2001.
[7] A. Helmy, M. Ismail, Substrate Noise Coupling in RFICs, Springer, 2008.
[8] S. M. Sze, Physics of Semiconductor Devices, Wiley, New York, 1981.
[9] S. Lee, K. Kim, T. H. Oh, I. Song, H. Shin, M. Kim, J.S. Rieh, “Suppression of Digital
Noise Coupling on LNA in 0.13-um RFCMOS Technology by Global Guard Rings,” in
Silicon Monolithic Integrated Circuits in RF Systems, 2008, pp. 206 - 209.
[10] T. L. Hsu, Y. C. Chen, H. C. Tseng, V. Liang, J. S. Jan, ”psub Guard Ring Design and
Modeling for the Purpose of Substrate Noise Isolation in the SOC Era,” IEEE
Electron Device Letters, vol. 26, no. 9, pp. 693 – 695, Sept, 2005.
[11] G. A. Rezvani, J. Tao, “substrate isolation in 0.18um CMOS Technology,” in Proc.
IEEE Int. Conf. Microelectronic Test Structures, April, 2005, pp. 133 – 136.
[12] W. K. Yeh, S. M. Chen, Y. K. Fang, ”substrate Noise-coupling Characterization and
Efficient suppression in CMOS technology,” IEEE Electron Device Letters, vol. 51, no.
5, pp. 817 – 819, May, 2004.
[13] P. C. Yeh, H. K. Chiou, C. Y. Lee, J. Yeh, D. Tang, J. Chern, ”An experimental study
on high-frequency substrate noise isolation in BiCMOS Technology,” IEEE Electron Device Letters, vol. 29, no. 3, pp. 255 - 258, Mar, 2008.
[14] S. Bronckers, G. Vandersteen, G. VanderPlas,Y. Rolain,“On the P+ guard ring sizing
strategy to shield against substrate noise,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium , pp. 753 – 756, June 2007.
[15] N. Checka, D.-D. Wentzloff, A. Chandrakasan, R. Reif,“The Effect of Substrate Noise
on VCO Performance,”IEEE Radio Frequency integrated Circuits (RFIC) Symposium ,
pp. 523 – 526, June, 2005.
[16] S. Bronckers, K.Scheir, G.VanderPlas, Y.Rolain ,”The impact of substrate noise on a
48-53 GHz mm-wave LC-VCO,” IEEE Silicon Monolithic Integrated Circuits in RF Systems, pp. 1 - 4, 2009.
[17] S. Bronckers, K. Scheir, G. Vander Plas, G. Vandersteen, Y. Rolain,” A Methodology
to Predict the Impact of Substrate Noise in AnalogRF Systems,” IEEE Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 11, pp. 1613 - 1626, November, 2009.
[18] D. Leenaerts and P. de Vreede, "Influence of substrate noise on RF performance," in
proceedings of the 26th European Solid-State Circuits Conference, pp. 328-331, 2000.
[19] C. Soens, C. Crunelle, P. Wambacq, G. Vandersteen, S. Donnay, Y. Rolain, M. Kuijk,
and A. Barel, "Characterization of substrate noise impact on RF CMOS integrated
circuits in lightly doped substrates," in Proceedings of the 20th IEEE Instrumentation
and Measurement Technology Conference, pp. 1303-1308, 2003.
[20] S. Hazenboom, T. Fiez, and K. Mayaram, "Digital noise coupling mechanisms in a 2.4
GHz LNA for heavily and lightly doped CMOS substrates," in Proceedings of the IEEE
2004 Custom Integrated Circuits Conference, pp. 367-370, 2004.
[21] D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental Result and
Modeling Techniques for Substrate Noise in Mixed.signal Integrated Circuits,”
IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 420-430, Apr. 1993.
[22] M. Werthen, I. Wolff, R. Keller,and W. Bischof, “Investigation of MMIC
Inductor Coupling Effect,” IEEE MTT-S International, vol.3, pp. 1793.1796, June
1997.
[23] A. O. Adan, M. Fukumi, K. Higashi, T. Suyma, M. Miyamoto, and M. Hayshi,
“Electromagnetic Coupling Effects in RFCMOS Circuits,” IEEE RFIC
Symposium, pp. 293-296, June 2002.
[24] Badaroglu, M., “Evolution of substrate noise generation mechanisms with CMOS
technology scaling” IEEE Trans. Circuits Syst. I, vol. 53, pp. 296 – 305, Feb. 2006.
[25] S. Lee, K. Kim, T.-H. Oh, I. Song, H. Shin, M. Kim, and J.-S. Rieh, ”Suppression of Digital Noise Coupling on LNA in 0.13-µm RFCMOS Technology by Global Guard Rings,” Silicon Monolithic Integrated Circuit in RF System, pp. 206-209, Jan. 2008.
[26] http://www.intel.com/technology/mooreslaw/

指導教授

辛裕明(Yue-ming Hsin)

審核日期

2010-7-20

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