以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：12

、訪客IP：13.58.247.31

姓名	劉育誠(Yu-Cheng Liu)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	應用於追蹤保持電路之高速寬頻放大器與毫米波主動集成天線之研究 (Research on high-speed broadband amplifiers for track-and-hold applications and millimeter-wave active integrated antennas)
相關論文	★ 微波及毫米波切換器及四相位壓控振盪器整合除三 除頻器之研製 ★ 微波低相位雜訊壓控振盪器之研製 ★ 高線性度低功率金氧半場效電晶體射頻混波器應用於無線通訊系統 ★ 砷化鎵高速電子遷移率之電晶體微波/毫米波放大器設計 ★ 微波及毫米波行進波切換器之研製 ★ 寬頻低功耗金氧半場效電晶體 射頻環狀電阻性混頻器 ★ 微波與毫米波相位陣列收發積體電路之研製 ★ 24 GHz汽車防撞雷達收發積體電路之研製 ★ 低功耗低相位雜訊差動及四相位單晶微波積體電路壓控振盪器之研究 ★ 高功率高效率放大器與振盪器研製 ★ 微波與毫米波寬頻主動式降頻器 ★ 微波及毫米波注入式除頻器與振盪器暨射頻前端應用 ★ 寬頻主動式半循環器與平衡器研製 ★ 雙閘極元件模型與微波及毫米波分佈式寬頻放大器之研製 ★ 銻化物異質接面場效電晶體之研製及其微波切換器應用 ★ 微波毫米波寬頻振盪器與鎖相迴路之研製
檔案	[Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載] 本電子論文使用權限為同意立即開放。 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中)	本篇論文所研究之主題為寬頻高速電路-寬頻分佈式放大器之設計並應用於追蹤-保持放大器，以及微波與毫米波主動式集成天線之設計。論文的第二章為使用砷化鎵製程製作之疊接式的分佈式寬頻放大器的分析與設計，使用之砷化鎵製程同時擁有高電子遷移率電晶體與異質接面雙載子電晶體(HBT)，包含了完整的分析模擬與實驗結果。章節中，對於分佈式放大器之增益級，針對使用兩種不同結構之電晶體組合的疊接架構(HEMT-HEMT, HEMT-HBT, HBT-HEMT, 與 HBT-HBT疊接架構)，所能達成的頻寬與增益進行比較與分析，以提升放大器的電路性能。藉由修正的m-導出式網路(m-dervied network)與使用電感提升的方式加入HEMT-HBT疊接式放大器進行設計，有效的加強分佈式放大器的頻寬與增益。在直流偏壓電路的設計上，使電路達到完全的整合在單晶片中，不須另外使用T型偏壓器(Bias-Tee)或使用其他的元件進行偏壓。本章所實作的分佈式放大器達成43.5 GHz的頻寬與8.5 dB的增益，且最大輸出功率1 dB壓縮點為8 dBm。此外，由12.5 Gbps速率的眼圖量測的結果顯示，本章所設計的分佈式放大器具有優良的傳輸品質。本章所設計之分佈式放大器達成了寬頻，具有良好的平坦度，低的群速度延遲，以及優良的傳輸品質。由於其優越的性能和砷化鎵製程具有大量生產的優點，此分佈式放大器適合應用在現代的高速資料通訊上。 在第三章中，將會介紹關於設計追蹤-保持放大器的基本概念。在第四章中，設計了兩個具有高無雜散動態範圍的高速追蹤-保持放大器，使用了先進的互補式金屬氧化物半導體(complementary metal-oxide-semiconductor, CMOS)製程進行設計，同時具有高速、且低功耗的特性。此外，將分佈式放大器的架構應用於追蹤-保持放大器的輸入級，將操作頻寬提升至19.6 GHz。章節中，藉由分析追蹤保持級的線性度與頻寬的分析，進一步提升追蹤保持放大器的無雜散動態範圍與線性度。藉由挑選適合的開關電晶體尺寸，增強其電晶體打開時的頻關以及擁有高的線性度。在輸入緩衝級的分析中，比較了共源極、疊接式、以及分佈式放大器等不同的架構，比較其增益大小與可達成的頻寬。第一個設計的追蹤-保持放大器使用65 nm CMOS製程，使用了串接共源極與疊接放大器架構作為輸入與輸出緩衝級，達成7 GHz的操作頻寬與40.9 dB的無雜散動態範圍。第二個追蹤-保持放大器使用90 nm CMOS製程實現，加入了分佈式放大器做為輸入緩衝級，達成了19 GHz的操作頻率以及44.5 dB的無雜散動態範圍。本章節所製作的追蹤-保持放大器具有寬頻的操作頻寬，高的無雜散動態範圍，高線性度，高速的取樣速率，密集簡潔的晶片面積，相當適合用於手持儀器。 第五章中，設計了兩個毫米波、振盪器型態的主動式集成天線，使用砷化鎵0.15-μm假型高速電子移動率電晶體(pHMET)製程進行實作。第一個主動集成式天線使用差動式振盪器結合平面式八木天線，兩個電路間使用50歐姆阻抗匹配進行設計。第二個主動式集成天線則是將天現改為迴路天線，並且將天線作為振盪器中的電感-電容槽。章節中，針對此類的設計與阻抗匹配方式進行分析與討論。本章設計的兩個主動式集成天線分別操作在69.7與40.7 GHz，其有效全向幅射功率(effective isotropic radiated power, EIRP)分別為-13.2與-2.7 dBm。本章所提出之設計毫米波主動式天線的方式，可進一步應用於簡易的毫米波無線個人區域網路的應用之中。
摘要(英)	Research on the broadband amplifiers, track-and-hold circuits, and active integrated antennas in microwave and millimeter-wave (MMW) are presented in this dissertation. Design and analysis of the broadband cascode distributed amplifiers (DAs) using GaAs heterojunction bipolar transistor (HBT) / high electron mobility transistor (HEMT) process are completely presented with experimented results in Chapter 2. The gain-bandwidth analysis of cascode gain cell is presented using HEMT-HEMT, HEMT-HBT, HBT-HEMT, and HBT-HBT configurations to improve circuit performance. A modified m-derived network and a HEMT-HBT cascode amplifier with inductive peaking technique are proposed to enhance the gain and bandwidth of the DA. The dc bias networks of the DA are fully integrated in a single chip without off-chip bias-T or bias components. The DAs are designed and fabricated achieve a bandwidth from DC to 43.5 GHz with average gain of 8.5 dB, and the Output power 1-dB compression point is 8 dBm. Moreover, the DA is successfully evaluated with an eye diagram measurement up to 12.5 Gbps, and demonstrates good transmission quality. The DAs achieves broad bandwidth, good flatness, low group delay and good transmission quality. The DAs are suitable in the modern high-speed data communications due to the superior performance and the mass-production MMIC process. The basic concept of the track-and-hold amplifier is introduced in Chapter 3. Two high-speed track-and-hold amplifiers (THAs) with high spurious-free dynamic range (SFDR) are presented in Chapter 4. The THAs are realized in advanced 65 and 90 nm CMOS processes with high speed and low dc power consumption. The DA is employed in the THAs as an input buffer, and the input bandwidth is highly improved up to 19.6 GHz. The analysis of linearity and bandwidth for the track-and-hold stage is presented to improve the SFDR and linearity. The device size of the switch is properly selected to enhance turn-on bandwidth and high linearity. The analysis of input buffer is addressed with common-source, cascode, and distributed gain stages. The first THA is designed using 65 nm CMOS process with common source and cascode stages as input and output buffers, and it demonstrates an input bandwidth of 7 GHz and a SFDR of 40.9 dB. The second THA is designed in 90 nm CMOS process with a DA as input buffer, and it demonstrates an input bandwidth of 19 GHz and a SFDR of 44.5 dB. The proposed THAs feature broad bandwidth, compact chip area, high SFDR, high linearity, and high sampling rate, and they are suitable in the hand-held instruments. Two MMW oscillation-type active integrated antennas (AIAs) are design and fabricated in the 0.15-μm GaAs pHEMT process presented in Chapter 5. The first AIA is composed of a differential voltage-controlled oscillator (VCO) and a planar-Yagi antenna, the impedance matching between the two components is 50 Ω. For the second AIA design, the antennas is designed using a loop antenna, and also the antenna is designed as an inductance-capacitance (LC) tank of the VCO. The impedance matching between the differential VCO and the loop antenna is addressed in Chapter 5. The operation frequencies of proposed AIAs are in 69.7 and 40.7 GHz, and the effective isotropic radiated powers (EIRPs) of -13.2 dBm and -2.7 dBm, respectively. The proposed methodology is suitable for the simple MMW wireless personal area network applications.
關鍵字(中)	★ 毫米波 ★ 微波 ★ 追蹤保持電路 ★ 主動集成式天線 ★ 分佈式 ★ 放大器	關鍵字(英)	★ millimeter-wave ★ microwave ★ track-and-hold ★ active integrated antenna ★ distributed ★ amplifier
論文目次	摘要 Abstract Table of Contents List of Figures List of Table Chapter 1 Introduction 1.1 Motivation 1.2 Literatures survey 1.3 Contributions 1.4 Dissertation Organization Chapter 2 Design and Analysis of Distributed Amplifiers 2.1 Introduction 2.2 Designed MMIC Process 2.3 GaAs 0.5 μm pHEMT cascode DA 2.4 GaAs 0.5 μm/2 μm BiHEMT cascode DA 2.5 Summary Chapter 3 Basic of Sampling and Sample-and-hold Circuit 3.1 Samplin 3.2 Specifications of Sample-and-hold Circuit 3.3 Common Circuit of Track-and-hold Circuit 3.4 Summarized to design a track-and-hold amplifier Chapter 4 Design and Analysis of Track-and-hold Circuits 4.1 Introduction 4.2 MMIC Process 4.3 Circuit Design and Analysis 4.4 65-nm CMOS track-and-hold amplifier 4.5 90-nm CMOS track-and-hold amplifier 4.6 Summary Chapter 5 Design and Analysis of Active Integrated Antennas 5.1 Introduction 5.2 Analysis of VCO and self-oscillation active antenna 5.3 GaAs 0.15-μm pHEMT Yagi-uda active integrated antenna 5.4 FR-4 self-oscillation active antenna test circuit 5.5 GaAs 0.15-μm pHEMT self-oscillation active integrated antenna 5.6 Summary Chapter 6 Conclusions Bibliography Publication List
參考文獻	[1] T. Shibata, S. Kimura, H. Kimura, Y. Imai, Y. Umeda, Y. Akazawa, “A design technique for a 60 GHz-bandwidth distributed baseband amplifier IC module, “ IEEE J. Solid State Circuits, vol. 39, no. 12, pp. 1537-1544, Dec. 1994. [2] K. W. Kobayashi, “Linearized darlington cascode amplifier employing GaAs PHEMT and GaN HEMT techonologies,” IEEE J. Solid-State Circuits, vol. 42, pp. 2116-2122, Oct. 2007. [3] K. W. Kobayashi, R. Esfandiari, M. E. Hafizi, D. C. Streit, A. K. Oki, L. T. Tran, D. K. Umemoto, M. E. Kim, “GaAs HBT wideband matrix distributed and darlington feedback amplifiers to 24 GHz,” IEEE Trans. Microw. Theory and Tech., vol.39, no.12, pp.2001-2009, Dec. 1991. [4] W. Ko, Y. Kwon, “High-gain direct-coupled matrix distributed amplifier using active feedback topology,” IEEE Compound Semiconductor Integrated Circuit Symp. Dig., Oct. 2004, pp. 309-312. [5] J. Shohat, I. D. Robertson, S. J. Nightingale, “10-Gb/s driver amplifier using a tapered gate line for improved input matching,” IEEE Trans. Microw. Theory and Tech. vol. 53, pp. 3115-3120, Oct. 2005. [6] M. Hafele, K. Beilenhoff, H. Schumacher, “GaAs distributed amplifiers with up to 350 GHz gain-bandwidth product for 40 Gb/s LiNbO3 modulator drivers,” European Microw. Conf., vol. 1, Oct. 2005. [7] C. Meliani, W. Heinrich, “True broadband technique for on-chip-series connection of TWAs using differential distributed amplifiers,” IEEE Microw. Wireless Compon. Lett., vol. 19, pp. 248-250, April 2009. [8] C. Meliani, M. Rudolph, W. Heinrich, “A 40 Gbps GaAs-HBT distributed amplifier with an over-fT cut-off frequency: analytical and experimental study,” in IEEE MTT-S International Microw. Symp. Dig., June 2005, pp.1857-1860. [9] G. Wolf, S. Demichel, R. Leblanc, R. Lefevre, G. Dambrine, and H. Happy,” A metamorphic GaAs HEMT distributed amplifier with 50 GHz bandwidth and low noise for 40 Gbits/s,” in IEEE MTT-S International Microw. Symp. Dig., 2005, pp. 2231-2233. [10] C. Meliani, G. Post, G. Rondeau, J. Decobert, W. Mouzannar, E. Dutisseuil, and R. Lefevre, “DC-92 GHz ultra-broadband high gain InP HEMT amplifier with 410 GHz gain-bandwidth product,” IEE Electronics Lett., vol. 20, no. 20, pp. 1175-1176, Sept. 2002. [11] T. Kraemer, C. Meliani, F. J. Schmueckle, J. Wuerfl, G. Traenkle, “Traveling-wave amplifiers in transferred substrate InP-HBT technology,” IEEE Trans. Microw. Theory and Tech., vol. 57, pp. 2114-2121, Sept. 2009. [12] K. Moez, M. Elmasry, “A 10dB 44GHz loss-compensated CMOS distributed amplifier,” IEEE International Solid-State Circuits Conference, pp. 548-621, Feb 2007. [13] M.-D. Tsai, H. Wang, J.-F. Kuan, and C.-S. Chang, “A 70GHz cascaded multi-stage Distributed amplifier in 90nm CMOS technology,” IEEE Int. Solid-State Circuit Conf. Dig., vol. 1, Feb. 2005, pp.402-403. [14] R.-C. Liu, T.-P. Wang, L.-H. Lu, H. Wang, “An 80GHz traveling-wave amplifier in a 90nm CMOS technology,” IEEE Int. Solid-State Circuit Conf. Dig., vol. 1, Feb. 2005, pp.154-155. [15] A. Boni, A. Pierazzi, C. Morandi, “A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS,” IEEE J. Solid-State Circuits, vol. 36, no. 02, pp. 195-203, Feb. 2001. [16] X. Li, W.-M. Kuo, Y. Lu, R. Krithivasan, J.D. Cressler, and A.J. Joseph, “A 5-bit, 18 GS/sec SiGe HBT track-and hold amplifier,” in 2005 IEEE Compound Semiconductor Integr. Circuit Symp., Oct. 2005, pp. 105-108. [17] H.-G. Wei, U-Fat Chio, Y. Zhu, S.-W. Sin, S.-P. U, R. P. Martins, “A rapid power-switchable track-and-hold amplifier in 90-nm CMOS,” IEEE Trans. Circuits Syst. II, Ex Briefs, vol. 57, no. 01, pp. 16-20, Jan. 2010. [18] J.-C. Chien, L.-H. Lu, “40-Gb/s high-gain distributed amplifiers with cascaded gain stages in 0.18-mm CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, pp 2715-2725, Dec. 2007. [19] J. Lee, A. Leven, J.S. Weiner, Y. Baeyens, Y. Yang, W.-J. Sung, J. Frackoviak, R.F. Kopf, and Y.-K. Chen, “A 6-b 12-GSamples/s track-and-hold amplifier in InP DHBT technology,” IEEE J. Solid-State Circuits, vol. 38, no. 06, pp. 1533-1539, June 2003. [20] Y. Bouvier, A. Ouslimani, A. Konczykowska, and J. Godin, “A 1-GSample/s, 15-GHz input bandwidth master–slave track-and-hold amplifier in InP DHBT technology,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 12, pp. 3181-3187, Dec. 2009. [21] Y. Bouvier, A. Ouslimani, A. Konczykowska, and J. Godin, “A 40 G samples/s InP-DHBT track-and-hold amplifier with high dynamic range and large bandwidth,” in 2012 8th Int. Symp. On Commun. Syst., Networks & Digital Signal Process., July 2012, pp. 1-4. [22] J. Deza, A. Ouslimani, A. Konczykowska, A. Kasbari, M. Riet, J. Godin, and G. Pailler, “A 50-GHz-small-signal-bandwidth 50 GSa/s Track&Hold amplifier in InP DHBT technology,” in 2012 IEEE MTT-S Int. Microw. Symp. Dig., June 2012, pp. 17-22. [23] J. Deza, A. Ouslimani, A. Konczykowska, A. Kasbari, and J. Godin, “A 4 GSa/s, 16-GHz input bandwidth master-slave track-and-hold amplifier in InP DHBT technology,” in 2012 20th Telecommun. Forum, Nov. 2012, pp. 502-505. [24] S. Daneshgar, Z. Griffith, M. Seo, M.J.W. Rodwell, “Low distortion 50 GSamples/s track-hold and sample-hold amplifiers,” IEEE J. Solid-State Circuits, vol. 49, no. 10, Jul. 2014. [25] J.Deza, A. Ouslimani, A. Konczykowska, A. Kasbari, J. Godin, G. Pailler, “70 GSa/s and 51 GHz bandwidth track-and-hold amplifier in InP DHBT process,” Electronics Lett., vol.49, pp. 388-389, Mar. 2013. [26] S. Shahramian, A. C. Carusone, and S. P. Voinigescu, “Design methodology for a 40-GSamples/s track and hold amplifier in 0.18-μm SiGe BiCMOS technology,” IEEE J. Solid-State Circuits, vol. 41, pp. 2233-2240, Sept. 2006. [27] X. Li, W.-M. L. Kuo, and J. D. Creeler, “A 40 GS/s SiGe track-and-hold amplifier,” in IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2008, Oct. 2008, pp. 1-4. [28] S. Shahramian, S. P. Voinigescu, and A. C. Carusone, “A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees,” IEEE J. Solid-State Circuits, vol. 44, pp. 1709-1720, June 2009. [29] M. Buck, M. Grözing, M. Berroth, M. Epp, and S. Chartier, “A 6 GHz input bandwidth 2 Vpp-diff input range 6.4 GS/s track-and-hold circuit in 0.25 μm BiCMOS,” in 2013 IEEE RFIC Symp. Dig., June 2013, pp. 159-162. [30] H. Orser, and A. Gopinath, “A 20 GS/s 1.2 V 0.13μm CMOS switched cascode track-and-hold amplifier,” IEEE Trans. Circuits Syst. II, Ex Briefs, vol 57, pp. 512-516, July 2010. [31] H.-L. Chen, S.-C. Cheng, B.-W. Chen, “A 5-GS/s 46-dBc SFDR track and hold amplifier,” in 2012 Int. Symp. on Intelligent Signal Processing and Communications Systems (ISPACS), 4-7 Nov. 2012, pp. 636-639. [32] G. Tretter, D. Fritsche, C. Carta, F. Ellinger, “10-GS/s track and hold circuit in 28 nm CMOS,” in 2013 Int. Semiconductor Conf. Dresden-Grenoble (ISCDG), Sept. 2013, pp. 1-3. [33] J. Proesel, G. Keskin, J.-O. Plouchart, L. Pileggi, "An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection," 2010 IEEE Custom Integrated Circuits Conf., Sept. 2010, pp. 1-4. [34] Y.-C. Liu, H.-Y. Chang, and K. Chen, “A 12 GB/s 3-GHz input bandwidth track-and-hold amplifier in 65 nm CMOS with 48-dB spur-free dynamic range,” in 2014 IEEE MTT-S Int. Microw. Symp. Dig., Florida, USA, Jun. 2014. [35] H. Dinc, P.E. Allen, “A 1.2 GSample/s double-switching CMOS THA with -62 dB THD,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp.848-861, March 2009. [36] S. Yamanaka, et al., “A 20-Gs/s track-and-hold amplifier in InP HBT technology,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 9, pp. 2334-2339, Sept. 2010. [37] T.D. Gathman, K.N. Madsen, J.C. Li, T.C. Oh, J.F. Buckwalter, “30.8 A 30GS/s double-switching track-and-hold amplifier with 19dBm IIP3 in an InP BiCMOS technology,” in IEEE Int. Solid-State Circuit Conf. Dig. of Techn. Papers, Feb. 2014, pp.1-3. [38] Simon Louwsma, Ed van Tuijl, Bram Nauta, Time-interleaved Analog-to-Digital Converters, Springer, Inc., 2011. [39] C.J.B. Fayomi, G.W. Roberts, M. Sawan, "Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization," in IEEE Int. Symp. on Circuits and Systems, vol. 3, May 2005, pp.2200-2203. [40] J.-S. Chen, M.-D. Ker, “Circuit performance degradation of switched-capacitor circuit with bootstrapped technique due to gate-oxide overstress in a 130-nm CMOS process,” IEICE Transaction on Electronics, pp.378-384, Mar. 2008. [41] S.H. Lewis, P.R. Gray, “A pipelined 5-Msample/s 9-bit analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 22, no. 6, pp. 954-961, Dec. 1987. [42] A. Shamim, L. Roy, G. Tarr,V. Levenets, N. Fong, “24 GHz differential integrated antennas in 10 Ω-cm bulk silicon,” Antennas and Propagation Society International Symposium, 2005, vol. 1A, pp. 536-539. [43] K. T. Chan, Y. D. Lin, C. Y. Chang, et al., “Integrated antennas on Si with over 100 GHz performance, fabricated using an optimized proton implantation process,” IEEE Microw. Compon. Lett., pp. 487-489, Nov. 2003. [44] Kihong Kim, Hyun Yoon, Kenneth K. O, “On-chip wireless interconnection with integrated antennas,” IEEE International Electron Devices Meeting, pp. 485-488, Dec 2000. [45] Kihong Kim, Kenneth K. O, “Characteristics of integrated dipole antennas on bulk, SOI, and SOS substrates,” IEEE Conf. on Interconnect Techn., June 1998, pp. 21-23. [46] I.S. Chen, H.K. Chiou, N.W. Chen, “V-Band on-chip dipole-based antenna,” IEEE Trans. Antennas Propag., vol 57, no 10, pp. 2853–2861, Oct. 2009. [47] M. Singer, K. M. Strohm, J.-F. Luy, E. M. Biel, “Active SIMMWIC-antenna for automotive applications,” IEEE Symp. on Microw., June 1997, pp.1265-1268. [48] Jenshan Lin; Itoh, T., "Active integrated antennas," IEEE Trans. Microw. Theory and Techn., vol.42, no.12, pp.2186-2194, Dec 1994. [49] Morteza Abbasi, S.E. Gunnarsson, N. Wadefalk, R. Kozhuharov, J. Svedin, S. Cherednichenko, I. Angelov, I. Kallfass, P. Leuther, H. Zirath, “Single-chip 220-GHz active heterodyne receiver and transmitter MMICs with on-chip integrated antenna,” IEEE Trans. Microw. Theory and Techn.,, vol.59, no.2, pp.466-478, Feb. 2011. [50] A.L. Amadjikpe, D. Choudhury, C.E. Patterson, B. Lacroix, G.E. Ponchak, J. Papapolymerou, “Integrated 60-GHz antenna on multilayer organic package with broadside and end-fire radiation,” IEEE Trans. Microw. Theory and Techn., vol.61, no.1, pp.303-315, Jan. 2013. [51] I-J. Chen, H. Wang, P. Hsu, “A V-band quasi-optical GaAs HEMT monolithic integrated antenna and receiver front end,” IEEE Trans. Microw. Theory Techn., vol. 51, No. 12, pp. 2461-2468, Dec. 2003. [52] Ya-Yun Lin, Cheng-Hsun Wu, Tzyh-Ghuang Ma, “Miniaturized self-oscillating annular Ring active integrated antennas,” IEEE Trans. Antennas Propag., vol.59, no.10, pp.3597-3606, Oct. 2011. [53] Seunggun Baek, Gang-Sik Lee, Kyunghaeng Lee, Yong Jee, “Multi-band active integrated antenna using Clapp oscillator circuit,” 2011 6th International Conf. on Telecommun. Systems, Services, and Applications (TSSA), 20-21 Oct. 2011, pp.69-72. [54] M.D. Upadhayay, A. Basu, M. P. Abegaonkar, S. K. Koul, “Active integrated antenna using BJT with floating base,” IEEE Microw. Compon. Lett., vol.23, no.4, pp.202-204, April 2013. [55] Cheng-Hsun Wu, Tzyh-Ghuang Ma, “Self-oscillating semi-ring active integrated antenna with frequency reconfigurability and voltage-controllability,” IEEE Trans. Antennas Propag., vol.61, no.7, pp.3880-3885, July 2013. [56] Cheng-Hsun Wu, Tzyh-Ghuang Ma, “Pattern-reconfigurable self-oscillating active integrated antenna with frequency agility,” IEEE Trans. Antennas Propag., vol.62, no.12, pp.5992-5999, Dec. 2014. [57] H.-K. Chiou, I.-S. Chen, Chen, W.-C., “High gain V-band active-integrated antenna transmitter using Darlington pair VCO in 0.13 μm CMOS process,” Electronics Letters, vol.46, no.5, pp.321-322, March 4 2010. [58] H.-Y. Chang, R.-Y. Hung, Y.-L. Yeh, K. Chen, S.-H. Wu, Y.-C. Wang, “An 86-92 GHz frequency shift keying transmitter with an integrated antenna in 0.5 μm E/D- PHEMT technology,” IEEE Microw. Compon. Lett., pp. 749-751, Nov. 2009. [59] S. Masuda, T. Takahashi, K. Joshin, “An over-110-GHz InP HEMT flip-chip distributed baseband amplifier with inverted microstrip line structure for optical transmission system,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 1479-1484, Sep. 2003. [60] J. Aguirre and C. Plett, “50-GHz SiGe HBT distributed amplifiers employing constant-k and m-derived filter sections,” IEEE Trans. Microw. Theory and Tech., vol. 52, no. 5, pp. 1573-1579, May 2004. [61] H.-Y. Chang, “Design of broadband highly linear IQ modulator using a 0.5-μm E/D-PHEMT process for millimeter-wave applications” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 7, pp. 491-493, July 2008. [62] H.-Y. Chang, Y.-S. Wu, and Y.-C. Wang, “A 38% tuning bandwidth low phase noise differential voltage controlled oscillator using a 0.5 μm E/D-PHEMT process,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 07, pp. 467-469, July 2009. [63] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., John Wiley & son, 2010, Chapter 7. [64] “Sonnet User’s Guide,” 12th ed. Sonnet Software, Inc., North Syracuse, NY, 2009. [65] B. S. Virdee, A. S. Virdee, and B. Y. Banyamin, Broadband Microwave Amplifiers, Artech House, 2004, Chapter 2. [66] D. M. Pozar, Microwave Engineering, second ed., John Wiley & son, 1998, Chapter 8. [67] A. S. Sedra, K. C. Smith, Microelectronic Circuits, 5th ed., New York: Oxford, 2004, Chapter 7. [68] S.-H. Weng, H.-Y. Chang, and C.-C. Chiong, “A DC-21 GHz low imbalance active balun using darlington cell technique for high speed data communications,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 11, pp. 728-730, Nov. 2009. [69] S. Galal, B. Razavi, “40-Gb/s amplifier and ESD protection circuit in 0.18-μm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 2389-2396, Dec. 2004. [70] J. Aguirre, C. Plett, P. Schvan, “A 2.4Vp-p output, 0.045-32.5 GHz CMOS distributed amplifier,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 427-430, June 2007. [71] Behzad Razavi, Principles of Data Conversion System Design, Willey-IEEE Press, 1994. [72] Walt Kester, MT-003 tutorial : Understand SINAD, ENOB, THD, THD+N, and SFDR so You Don’t Get Lost in the Noise Floor, Analog Devices, Inc.. [73] Walt Kester, MT-017 tutorial : Oversampling Interpolating DACs, Analog Devices, Inc.. [74] C. Pearson, High-speed, analog-to-digital converter basics, Texas Instrument Application Report, Jan. 2011. [75] P. Poshala, Why oversample when undersampling can do the job?, Texas Instrument Application Report, Jun. 2013. [76] Hank Zumbahlen, Basic Liner Design, Analog Devices, Inc., 2007. [77] Walt Kester, Analog-Digital Conversion, Analog Devices, Inc., 2004. [78] J. C. Jensen and L. E. Larson, “A broadband 10-GHz track-and-hold in Si/SiGe HBT technology,” IEEE J. Solid-State Circuits, vol. 36, pp. 325–330, 2001. [79] C. Fiocchi, U. Gatti, and F. Maloberti, “Design issues on high-speed high-resolution track-and-holds in BiCMOS technology,” Proc. Inst. Elect. Eng.—Circuits, Devices Syst., vol. 147, no. 2, pp. 100–106, Apr. 2000. [80] P. Vorenkamp, Eindhoven, Netherlands Philips Res. Lab., J.P.M. Verdaasdonk, “Fully bipolar, 120-Msample/s 10-b track-and-hold circuit,” IEEE J. Solid-State Circuits, vol. 27, no. 7, pp. 988-992, Jul. 1992. [81] H. Aggrawal, A. Babakhani, "A 40GS/s Track-and-Hold amplifier with 62dB SFDR3 in 45nm CMOS SOI," in IEEE MTT-S International Microw. Symp. Dig., June 2014, pp. 1-3. [82] Y.-M. Lin, B. Kim, and P. R. Gray, “A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS,” IEEE J. Solid-State Circuits, vol. 26, no. 04, pp. 628-636, Apr. 1991. [83] H.-Y. Chang, Y.-C. Liu, S.-H. Weng, C.-H. Lin, Y.-L. Yeh, and Y.-C. Wang, “Design and analysis of a DC–43.5-GHz fully integrated distributed amplifier using GaAs HEMT–HBT cascode gain stage,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 2, pp. 443-455, Feb. 2011. [84] F. Centurelli, P. Monsurro, A. Trifiletti, “A model for the distortion due to switch on-resistance in sample-and-hold circuits,” in 2006 IEEE Int. Symp. on Circuits and Systems, May 2006. pp. 21-24. [85] C.-C. Shen, H.-Y. Chang, and Y.-C. Wang, “A Monolithic 3.5-to-6.5 GHz GaAs HBT-HEMT/common-emitter and common-gate stacked power amplifier” IEEE Microw. Compon. Lett., vol. 22, no. 09, pp. 474-476, Sept. 2012. [86] H.-Y. Chang, C.-H. Lin, Y.-C. Liu, Y.-L. Yeh, K. Chen, and S.-H. Wu, “65 nm CMOS dual-gate device for Ka-band broadband low noise amplifier and high-accuracy quadrature voltage controlled oscillator,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 06, pp. 2402-2413, Jun. 2013. [87] Y.-A. Lin, Y.-C. Yeh, Y.-C. Liu and H.-Y. Chang, “A 55-dB SFDR 16-GS/s track-and-hold amplifier in 0.18 μm SiGe using differential feedthrough cancellation technique,” in 2016 IEEE MTT-S Int. Microw. Symp. Dig., San Francisco, USA, May. 2016. [88] PPC-100 Series Wireless LAN Bridge Brochure ElvaLin LLC Corporation. Solon, OH, Jun. 2004. [89] H.-Y. Chang, and C.-Y. Chan, “A low loss high isolation DC-60 GHz SPDT traveling-wave switch with a body bias technique in 90 nm CMOS process,” IEEE Microw. Compon. Lett., vol. 20, no. 02, pp. 82-84, Feb. 2010. [90] C. A. Balanis, Antenna theory analysis and design, 3rd ed. John Wiley & Sons, 2005. [91] J. E. Storer,“ Impedance of Thin-Wire Loop Antennas,” Amer. Inst. Elec. Eng. Trans., vol. 75, pp. 606-619, Nov. 1956. [92] K. Chang, RF and Microwave Wireless Systems, John Wiley & Sons, 2000.
指導教授	張鴻埜(Hong-Yeh Chang)	審核日期	2016-6-20
推文	facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu
網路書籤	Google bookmarks   del.icio.us   hemidemi   myshare