使用於生醫訊號的三角積分調變器

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姓名

戴邦傑(Pong-Kit Tai) 查詢紙本館藏

畢業系所

電機工程學系在職專班

論文名稱

使用於生醫訊號的三角積分調變器
(Sigma-Delta Modulator for Biomedical Signal Processing)

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摘要(中)

摘要
最近，快速成長的生物醫學電子市場，需要低功耗和低電壓[1]，[2]。由於電池用於可擕式生物設備最多。通過低功耗的結構使電池壽命延長是非常重要的。如在數位助聽器應用中，通常是由電池鋅空氣，並應提供10小時或至少兩個星期的使用壽命[3]。此外，數位助聽器寬動態範圍的要求，高性能，更可編程性和小型化。因此，要實現低功耗，高性能和可編程性，擴大電池壽命，並提供給用戶方便。
由於低振幅的生物醫學信號，高解析度和低功耗的類比至數位轉換器（ADC）非常重要。 Σ-△調製器在解析度和功耗性都能好。在這篇論文中，Σ-Δ調製器（SDM）使用在生物醫學電子系統。基本上，開關電容（SC）的技術和前饋（FF）的技術可同時實現在SDM的。這次的SDM是用台積電0.18um 1P6M CMOS技術來實現。信號寬為10 kHz，其取樣時鐘頻率為2.56 MHz的即過採樣比（OSR）是等於128。因此，它可以實現信號與雜訊及失真比（SNDR）為75.75分貝，高於10位元解析度。此外，功率消耗約為358uW, 在12位解析度下運行和動態範圍是85分貝和1.8V電源供應下。
基本上，SDM的ADC具有一個類比SDM和一個數位取樣濾波器。因此，我們可以整合兩個SDM與一個數字取樣濾波器。然後我們就可以輕鬆地監測2個生物醫學信號和保存了整個晶片的面積。
最近，快速成長的生物醫學電子市場，需要低功耗和低電壓。本文所設計之電路是使用三角積分調變器 (SDM)作為生物醫學電子用途。基本上，開關電容（SC）技術和向前回饋（FF）技術也可以同時被使用。本文對SDM進行模擬和以台積電 0.18微米1P6M CMOS製程技術來實現。此外輸入信號頻寬為 0〜10千赫時。取樣時脈速率為 2.56兆赫即（OSR）是等於 128。信號與雜訊及失真比（SNDR）為75.75分貝。二階三角積分調變器(SDM)的模擬結果是大於10位元的分辨率。在12位元的分辨率運行下功率消耗約 358uW。在1.8V的電源供應下，有85dB的動態範圍。

摘要(英)

Abstract
Recently, the rapid expansion of the biomedical-electronic market has necessitated low-power and low-voltage biomedical systems [1], [2]. Since battery power is used for most of the portable biomedical devices. Expanding battery lifetime through the topology of low power dissipation systems is very crucial. In the digital hearing-aid applications, the battery is typically made of zinc–air and should offer a life span of at least two weeks at 10 hours use per day [3]. Moreover, the digital hearing aid requires wide dynamic range, high performance, more programmability, and small form factor. Hence, it is necessary to achieve low power dissipation, high performance, and programmability to expand battery lifetime and to offer convenient hearing to the users.
Due to low-amplitude and non-stationary properties of biomedical signals, high resolution and low-power consumption are necessary for the analog-to-digital (A/D) convector (ADC). Sigma-Delta Modulator has good performance in the resolution and power consumption. In this thesis, Sigma-Delta Modulator (SDM) for a biomedical electronic system is proposed. Basically, the switched-capacitor (SC) technique and the Feedforward(FF) technique can be used to implement SDM. The proposed SDM was simulated with TSMC 0.18 ?m 1P6M CMOS technologies. The signal bandwidth is 10 KHz and its clock rate is 2.56 MHz i.e. the over-sampling ratio (OSR) is equal to 128. Hence, it can achieve 75.75 dB signal-to-noise and distortion ratio (SNDR), and higher than 10 bits resolution in 2nd orders SDM. Moreover, the power consumption is about 358 ?W in 12 bits resolution under normal operation and the dynamic range is 85 dB with a single 1.8V power supply.
Basically, an SDM ADC consists of an Analog SDM and Digital Decimation filter. Therefore, we can take the advantage of low power consumption of the implanted SDM to integrate two SDM adaptively with one digital decimation filter. Then we can easily to monitor 1 or 2 biomedical signals at the sample time and save the total chip area.

關鍵字(中)

★ 三角積分調變器
★ 生醫訊號

關鍵字(英)

★ Biomedical Signal
★ Sigma-Delta Modulator

論文目次

Contents
摘要…………………………………………………………….v
Abstract………………………………………………………….vi
致謝……………………………………………………………vii
List of figures………………...………………………………….xi
List of tables……………………………….…………………..xiii
Chapter 1 Introduction……………………………………1
1-1 Introduce…………………………………………....1
1-2 Structure of Thesis………………………………….2
Chapter 2 Basic Theories of an SDM………………….…3
2-1 Nyquist-Rate Data Conversion……………………..3
2-2 Quantization error…………………………………..7
2-3 Over-Sampling Topology…………………………11
2-4 Noise Shaping Topology………………………….13
2-5 1st order Sigma Delta Modulator………………….15
2-6 2nd order Sigma Delta Modulator…………………17
2-7 High order Sigma Delta Modulator……………….19
Chapter 3 System Design and simulation…….………...23
3-1 System design flow plan…………………………..26
3-2 Sigma Delta Modulator System Model…………...27
3-3 System simulation…………………………………28
3-4 System parameters on the circuitdesign…….…….32
Chapter 4 Implement and design of SDM………….…..40
4-1 System design and implement………….…………40
4-2 Switch Cap mode integrator technique……………44
4-2.1 The topology of integrator design, it will not be effected by parasitic cap ……………..…….....44
4-2.2 Op Amplify design……………………………45
4-2.3 Comparator design…………………………….52
4-2.4 Clock Generator design……………………….53
4-2.5 Circuit simulation result………………………55
Chapter 5 Layout planning and Measurement …….….60
5-1 Layout planning and Considering…………….…..60
5-2 Measurement Considering………………………...61
5-2.1 PCB design……………………………………61
5-2.2 Instrument issues for measurement……….…..63
5-3 Measurement Result……………………………....65
Chapter 6 Conclusions and Future works……………..69
6-1 Conclusions………………………………..……...69
6-2 Future works………………………………………69
Reference Paper……………………………………………...70

參考文獻

Reference Paper
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指導教授

薛木添(Muh-Tian Shiue)

審核日期

2010-12-13

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