以掃描式電容顯微鏡研究硼離子在矽基板中的瞬態增強擴散行為

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：122

、訪客IP：3.144.36.141

姓名

陳飛白(Fei-bai CHEN) 查詢紙本館藏

畢業系所

物理學系

論文名稱

以掃描式電容顯微鏡研究硼離子在矽基板中的瞬態增強擴散行為
(Investigation of Boron Transient Diffusion inSub-micron Patterned Silicon byScanning Capacitance Microscopy)

相關論文

★ 細菌地毯微流道中的次擴散動力學	★ Role of strain in the solid phase epitaxial regrowth of dopant and isovalent impurities co-doped silicon
★ hydrodynamic spreading of forces from bacterial carpet	★ What types of defects are created on supported chemical vapor deposition grown graphene by scanning probe lithography in ambient?
★ 應變及摻雜相互對以磷離子佈植之碳矽基板的固態磊晶成長動力學之研究	★ 雜質在假晶型碳矽合金對張力之熱穩定性影響
★ Revisiting the role of strain in solid-phase epitaxial regrowth of ion-implanted silicon	★ 利用選擇性參雜矽基板在石墨稀上局部陽極氧化反應
★ Thermal stability of supersaturated carbon incorporation in silicon	★ 氧化銅上的石墨烯在快速化學氣相沉積過程中的成核以及成長動力學
★ Reduction dynamics of locally oxidized graphene	★ 微小游泳粒子在固定表面的聚集現象
★ Role of impurities in semiconductor: Silicon and ZnO substrate	★ The growth of multilayer graphene through chemical vapor deposition
★ Characteristic of defect generated on graphene through pulsed scanning probe lithography	★ non

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

隨著積體電路零件縮小至微/奈米尺度，啟動元件所需的臨界電壓愈
來愈容易受到細微環境因素的影響。在同一片晶圓上，由設計的圖樣
差異所引起的臨界電壓差異現象稱之為系統化臨界電壓變異。微/奈
米尺度下的載子分布是影響臨界電壓的關鍵因素。
我們設計一套系統化實驗流程，成功取得佈植區間從0.3 到 5 微米
的二維載子分布，並以人口成長模型為基準，提出一個非線性方程式，
模擬結果相當符合實驗數據。
我們設計一系列長條(一維)和方塊(二維)的離子佈植區域，在熱退火
製程之後，以平面掃描式電容顯微鏡觀測二維載子分布。透過比對佈
植窗口與實驗結果，我們得到一系列載子瞬態增強擴散長度。實驗數
據顯示(1)擴散長度隨著尺度縮小而減少以及(2)硼原子在方塊區域
內的擴散長度較在長條區域內為長。我們的模型顯示 (1)在大尺寸的
佈植區域有較多的間隙矽原子幫助擴散以及(2)間隙矽原子由離子佈
植的邊界射出，方塊和長條分別具有五個和三個維度的佈植邊界；方
塊內的硼原子與間隙矽原子的結合率較高，因此擴散得更多。簡單來
說，我們首先研究了系統化佈植區域內的瞬態增強擴散，並更進一步
的證實尺度和維度是兩項影響瞬態增強擴散的重要因素。

摘要(英)

Current microelectronics chip can be composed of thousands of microarrays
that contain up to millions of physically identical transistors layout
in vastly different micro-environment. Systematic threshold voltage
(Vth) variation due to the detailed difference in the microenvironment has
been shown in many electrical assessments.
In this work, we have designed an experimental platform for investigating
the dependence of dimensionality in two dimensional boron diffusion
lengths (Ldi f f ). We systematically vary the ion implantation window
length scales in both length (l) and width (w) directions using photolithography
process. The two dimensional Ldi f f are measured with
plane view scanning capacitance microscopy (SCM). The Ldi f f in width
shrunk patterns exhibit stronger diffusion, especially in ion implantation
windows with larger l, namely, boron transient diffusion roll-off.
This observation suggest there is effectively more interstitial (Is) sources
within the proximity of B-Is interaction range during annealing and lead
to more significant transient enhanced diffusion (TED) at larger confinements.
The normalized Ldi f f for ion implantation boundaries length
scales ranging from 0.3 micron to 5 micron shows five folds difference.
The normalized curves for both categories of patterns overlap, indicating
similar physical mechanism in play for the two cases.
We have developed a non-linear logistics model. We can successfully
fit the experimental data with the above model by considering only the
difference in dimensionality. In particular, we found a 3/5 ratio for the
linear growth coefficients of effective Is supersaturation with respect to
the ion implantation boundary dimensions between the two patterns. We
relate this coefficient ratio to number of interstitial injection boundaries
available within B-Is interaction range.

關鍵字(中)

★ 瞬態增強擴散
★ 臨界電壓
★ 掃描式電容顯微鏡

關鍵字(英)

★ Scanning Capacitance Microscopy
★ logistics model
★ boron diffusion in silicon
★ transient enhanced diffusion
★ Threshold voltage

論文目次

1 Introduction 1
2 Background 5
2.1 Introduction of semiconductor . . . . . . . . . . . . . . . . . . . . . 6
2.1.1 The intrinsic silicon . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2 The extrinsic silicon . . . . . . . . . . . . . . . . . . . . . . 10
2.2 The Si based devices . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1 The p-n junction . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 Metal oxide semiconductor field effect transistor (MOSFET) . 13
2.3 Manufacturing process . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1 Photolithography . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.2 Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.3 Doping process . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.4 Post-implantation Annealing . . . . . . . . . . . . . . . . . 20
2.4 Challenges of shrinking devices . . . . . . . . . . . . . . . . . . . . 21
3 Literature survey 26
3.1 Normal diffusion and Fick’s law . . . . . . . . . . . . . . . . . . . . 27
3.2 A glance at transient enhancement diffusion (TED) . . . . . . . . . . 28
3.3 Historical survey . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4 The mechanisms of TED . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5 TED variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5.1 Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5.2 Implanted dose . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.3 Time evolution . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.4 Oxidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5.5 Co-implantation . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6 The plus-one model . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.7 The size effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.8 Variation issues at nano-scale . . . . . . . . . . . . . . . . . . . . . . 40
3.8.1 Systematic layout pattern variation . . . . . . . . . . . . . . . 40
3.8.2 Random dopant fluctuation . . . . . . . . . . . . . . . . . . 42
4 Experimental methods 44
4.1 Evolution of measurement . . . . . . . . . . . . . . . . . . . . . . . 44
4.2 SCM Working Principle . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2.1 Working Principle . . . . . . . . . . . . . . . . . . . . . . . 52
4.2.2 SCM signal analysis . . . . . . . . . . . . . . . . . . . . . . 57
5 Experimental results and discussions 59
5.1 Plane view sample preparation for SCM . . . . . . . . . . . . . . . . 59
5.1.1 Clean process . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.1.2 Etching curve . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2 SCM parameters tuning process . . . . . . . . . . . . . . . . . . . . 62
5.3 Dimensionality and size effects . . . . . . . . . . . . . . . . . . . . . 65
5.3.1 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.3.2 The experimental results . . . . . . . . . . . . . . . . . . . . 70
5.3.3 The logistics model for population growth . . . . . . . . . . . 73
5.3.4 The improved logistics model in our work . . . . . . . . . . 74
6 Conclusion 78
7 Bibliography 81

參考文獻

[1] F.Giannazzo. Scanning capacitance microscopy of semiconducting materials,
PhD thesis, Universita’ Degli Studi Di Catania, 2002.
[2] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. Wiley Interscience, New
York 1981.
[3] J.F. Gibbons, Proc. IEEE 60, 1062 (1972).
[4] F. Giannazzo, F. Pirolo, V. Raineri, and V. Privitera, Appl. Phys. Lett. 78, 598
(2001).
[5] Hong Xiao, Introduction of Semiconductor Manufacturing Technology, Prentice
Hall. Inc., United States 2000
[SRIM] The Stopping and Range of Ions in Matter, http://www.srim.org/
[6] W. K. Hofker, H.W.Werner, D. P. Oosthoek, and H. A. M. de-Grefte, Appl. Phys.
Lett. 2, 165 (1973).
[7] C. L. Claeys, G. J. Declerck, and R. J. Van-Overstraeten, Rev. Phys. Appl. 13,
797 (1978).
[8] H. Bracht, MRS Bull. 25, 6 (2000).
[9] N. Cowern and C. Rafferty, MRS Bull. 25, 39 (2000).
[10] M. D. Giles, Appl. Phys. Lett. 62, 1940 (1993).
[11] A. E. Michel, W. Rausch, P. A. Ronsheim, and R. M. Kastl, Appl. Phys. Lett. 50,
416 (1987).
[12] N. E. B. Cowern, J. T. F. Janssen, and H. F. F. Jos, J. Appl. Phys. 68, 6191 (1990).
[13] A. E. Michel, W. Rausch, P. A. Ronsheim, and R. M. Kastl, Appl. Phys. Lett. 50,
416 (1987).
[14] N. E. B. Cowern, M. Jaraiz, F. Cristiano, A. Claverie, and G. Mannino, Tech. Dig.
Int. Electron Devices Meet. 333 (1999).
[15] H. J. Gossmann, C. S. Rafferty, H. S. Luftman, F. C. Unterwald, T. Boone, and J.
M. Poate, Appl. Phys. Lett. 63, 639 (1993).
[16] D. Skarlatos et al:, J. Appl. Phys. 97, 113534 (2005).
[17] M. D. Giles, Appl. Phys. Lett. 62, 1940 (1993).
[18] M. D. Giles, J. Electrochem. Soc. 138, 1160 (1991).
[19] The International Technology Roadmap for Semiconductors, http:// public.
itrs.net.
[20] F. Giannazzo, F. Pirolo, V. Raineri, and V. Privitera, Appl. Phys. Lett. 78, 598
(2001).
[21] E. Bruno, S. Mirabella, G. Impellizzeri, F. Pirolo, F. Giannazzo, V. Raineri, and
E. Napolitani, Appl. Phys. Lett. 87, 133110 (2005).
[22] F. Giannazzo et al:, J. Vac. Sci. Technol. B 24, 468 (2006).
[23] E. G. Roth, O. W. Holland, V. C. Venezia, and B. Nielsen, J. Electron. Mater. 26,
1349 (1997).
[24] K. C. Ku, C. F. Nieh, J. Gong, L. P. Huang, Y. M. Sheu, C. C. Wang, C. H. Chen,
H. Chang, L. T. Wang, T. L. Lee, S. C. Chen, and M. S. Liang, Appl. Phys. Lett.
89, 112104 (2006).
[25] R.G. Mazur and P.H. Dickey, J. Electrochem. Soc. 113, 225 (1966).
[26] Dieter K. Schroder, Semiconductor Material and Device Characterization,
Wiley-Interscience, New York 2006.
[27] Y. Martin, D.W. Abraham, and Kumar Wickramasinghe, Appl. Phys. Lett. 52,
131103 (1988).
[28] F. Giannazzo, S. Mirabella, D. De Salvador, E. Napolitani, A. Terrasi, A. Carnera,
A. V. Drigo, and F. Pirolo, Phys. Rev. B 66, 161310 (2002).
[29] Masafumi Miyamoto, Hiroyuki Ohta, Yukihiro Kumagai, Yasuo Sonobe,
Kousuke Ishibashi, and Yasushi Tainaka, IEEE Trans. Electron Devices 51, 3,
(2004).
[30] N. E. B. Cowern, P. C. Zlam, P. C. van der Sluis, D. J. Gravesteijn, and W. B.
Boer, Phys. Rev. Lett. 72, 2585 (1994).
[31] Yi-Ming Sheu, Sheng-Jier Yang, Chih-ChiangWang, Chih-Sheng Chang, Li-Ping
Huang, Tsung-Yi Huang, Ming-Jer Chen, IEEE Trans. Electron Devices 52, 1
(2005).
[32] Kelin Kuhn et al:,Intel® Technology Journal, 12, 01 (2008).

指導教授

溫偉源(Wei-yen WOON)

審核日期

2011-7-22

推文