|| J. U. Knickerbocker, “3D Integration & Packaging Challenges with through-silicon-vias (TSV)”, (2012).|
 K. Sakuma, P. S. Andry, C. K. Tsang, S. L. Wright, B. Dang, C. S. Patel, B. C. Webb, J. Maria, E. J. Sprogis, S. K. Kang, R. J. Polastre, R. R. Horton, and J. U. Knickerbocker, “3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections”, IBM Journal of Research and Development 52, 611 (2008).
 H. Y. You, Y. S. Lee, S. K. Lee, and J. S. Kang, “Reliability of 20μm micro bump interconnects”, Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, 608 (2011).
 D. Amir and C. E. Bauer, “3D Packaging, Interconnection & Assembly”, (2013).
 A. Ostmann, A. Neumann, S. Weser, E. Jung, L. Bottcher, and H. Reichl, “Realization of a stackable package using chip in polymer technology”, Polymers and Adhesives in Microelectronics and Photonics, 2002. POLYTRONIC 2002. 2nd International IEEE Conference on, 160 (2002).
 H. Braunisch, S. N. Towle, R. D. Emery, H. Chuan, and G. J. Vandentop, “Electrical performance of bumpless build-up layer packaging”, Electronic Components and Technology Conference, 2002. Proceedings. 52nd, 353 (2002).
 K. S. Kao, S. T. Wu, Y. Po. Hung, T. C. Chang, R. S. Cheng, and T. H. Chen, “Application of numerical analysis to the reliability assessment of a novel package on package (PoP) structure for memory stacking”, Microsystems Packaging Assembly and Circuits Technology Conference (IMPACT), 2010 5th International, 1 (2010).
 P. Palm, J. Moisala, A. Kivikero, R. Tuominen, and A. Iihola, “Embedding active components inside printed circuit board (PCB) - a solution for miniaturization of electronics”, Advanced Packaging Materials: Processes, Properties and Interfaces, 2005. Proceedings. International Symposium on, 1 (2005).
 B. Dang, S. L. Wright, P. S. Andry, E. J. Sprogis, C. K. Tsang, M. J. Interrante, B. C. Webb, R. J. Polastre, R. R. Horton, C. S. Patel, A. Sharma, J. Zheng, K. Sakuma, and J. U. Knickerbocker, “3D chip stacking with C4 technology”, IBM Journal of Research and Development 52, 599 (2008).
 N. Koyanagi, H. Kurino, K. W. Lee, K. Sakuma, N. Miyakawa, and H. Itani, “Future system-on-silicon LSI chips”, Ieee Micro 18, 17 (1998).
 K. Sakuma, K. Sueoka, S. Kohara, K. Matsumoto, H. Noma, T. Aoki, Y. Oyama, H. Nishiwaki, P. S. Andry, C. K. Tsang, J. U. Knickerbocker, and Y. Orii, “IMC bonding for 3D interconnection”, Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th, 864 (2010).
 K. N. Chen, S. H. Lee, P. S. Andry, C. K. Tsang, A. W. Topol, Y. M. Lin, J. Q. Lu, A. M. Young, I. Meikei, and W. Haensch, “Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits”, Electron Devices Meeting, 2006. IEDM ′06. International, 1 (2006).
 A. Munding, H. Hübner, A. Kaiser, S. Penka, P. Benkart, and E. Kohn, “Cu/Sn Solid–Liquid Interdiffusion Bonding” in “Wafer Level 3-D ICs Process Technology”, edited by C. S. Tan, R. J. Gutmann, and L. R. Reif (Springer US, 2008), 1 (2008).
 T. Laurila, V. Vuorinen, and J. K. Kivilahti, “Interfacial reactions between lead-free solders and common base materials”, Materials Science and Engineering: R: Reports 49, 1 (2005).
 P. S. Ho, G. T. Wang, M. Ding, J. H. Zhao, and X. Dai, “Reliability issues for flip-chip packages”, Microelectronics Reliability 44, 719 (2004).
 K. Zeng and K. N. Tu, “Six cases of reliability study of Pb-free solder joints in electronic packaging technology”, Materials Science and Engineering: R: Reports 38, 55 (2002).
 C. E. Ho, S. C. Yang, and C. R. Kao, “Interfacial reaction issues for lead-free electronic solders” in “Lead-Free Electronic Solders” (Springer US, 2007), 155 (2007).
 A. Klumpp, R. Merkel, P. Ramm, J. Weber, and R. Wieland, “Vertical System Integration by Using Inter-Chip Vias and Solid-Liquid Interdiffusion Bonding”, Japanese Journal of Applied Physics 43, L829 (2004).
 R. Johannessen, M. Taklo, and M. F. Sunding, “SnAg Microbumps for MEMS-Based 3-D Stacks”, Advanced Packaging, IEEE Transactions on 32, 683 (2009).
 S. Bader, W. Gust, and H. Hieber, “Rapid formation of intermetallic compounds interdiffusion in the Cu-Sn and Ni-Sn systems”, Acta Metallurgica et Materialia 43, 329 (1995).
 H. Y. Son, G. J. Jung, B. J. Park, and K. W. Paik, “A Study on the Thermal Reliability of Cu/SnAg Double-Bump Flip-Chip Assemblies on Organic Substrates”, Journal of Electronic Materials 37, 1832 (2008).
 B. J. Kim, G. T. Lim, J. Kim, K. Lee, Y. B. Park, H. Y. Lee, and Y. C. Joo, “Intermetallic Compound Growth and Reliability of Cu Pillar Bumps Under Current Stressing”, Journal of Electronic Materials 39, 2281 (2010).
 G. T. Lim, B. J. Kim, K. Lee, J. Kim, Y. C. Joo, and Y. B. Park, “Temperature Effect on Intermetallic Compound Growth Kinetics of Cu Pillar/Sn Bumps”, Journal of Electronic Materials 38, 2228 (2009).
 R. Labie, P. Limaye, K. W. Lee, C. J. Berry, E. Beyne, and I. De Wolf, “Reliability testing of Cu-Sn intermetallic micro-bump interconnections for 3D-device stacking”, Electronic System-Integration Technology Conference (ESTC), 2010 3rd, 1 (2010).
 J. F. Li, P. A. Agyakwa, and C. M. Johnson, “Interfacial reaction in Cu/Sn/Cu system during the transient liquid phase soldering process”, Acta Materialia 59, 1198 (2011).
 Y. W. Wang, S. H. Chae, R. Dunne, Y. Takahashi, K. Mawatari, P. Steinmann, T. Bonifield, J. Tengfei, J. Im, and P. S. Ho, “Effect of intermetallic formation on electromigration reliability of TSV-microbump joints in 3D interconnect”, Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, 319 (2012).
 Y. W. Wang, S. H. Chae, J. Im, and P. S. Ho, “Kinetic study of intermetallic growth and its reliability implications in Pb-free Sn-based microbumps in 3D integration”, Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd, 1953 (2013).
 F. Y. Ouyang, W. C. Jhu, and T. C. Chang, “Thermal-gradient induced abnormal Ni3Sn4 interfacial growth at cold side in Sn2.5Ag alloys for three-dimensional integrated circuits”, Journal of Alloys and Compounds 580, 114 (2013).
 J. R. Lloyd, N. A. Connelly, X. He, K. J. Ryan, and B. H. Wood, “Fast diffusers in a thermal gradient (solder ball)”, Microelectronics Reliability 50, 1355 (2010).
 L. Meinshausen, K. Weide-Zaage, and H. Frémont, “Migration induced material transport in Cu–Sn IMC and SnAgCu microbumps”, Microelectronics Reliability 51, 1860 (2011).
 C. C. Lee, P. J. Wang, and J. S. Kim, “Are Intermetallics in Solder Joints Really Brittle?”, Electronic Components and Technology Conference, 2007. ECTC ′07. Proceedings. 57th, 648 (2007).
 K. J. Zeng, R. Stierman, T. C. Chiu, D. Edwards, K. Ano, and K. N. Tu, “Kirkendall void formation in eutectic SnPb solder joints on bare Cu and its effect on joint reliability”, Journal of Applied Physics 97, 024508 (2005).
 T. C. Chiu, K. Zeng, R. Stierman, D. Edwards, K. Ano, and K. N. Tu, “Effect of thermal aging on board level drop reliability for Pb-free BGA packages”, Electronic Components and Technology Conference, 2004. Proceedings. 54th, 1256 (2004).
 C. F. Tseng and J. G. Duh, “The influence of Pd on growth behavior of a quaternary (Cu,Ni,Pd)6Sn5 compound in Sn–3.0Ag–0.5Cu/Au/Pd/Ni–P solder joint during a liquid state reaction”, Journal of Materials Science 48, 857 (2012).
 C. F. Tseng, T. K. Lee, G. Ramakrishna, K. C. Liu, and J. G. Duh, “Suppressing Ni3Sn4 formation in the Sn–Ag–Cu solder joints with Ni–P/Pd/Au surface finish”, Materials Letters 65, 3216 (2011).
 I. T. Wang, J. G. Duh, C. Y. Cheng, and J. Wang, “Interfacial reaction and elemental redistribution in Sn3.0Ag0.5Cu–xPd/immersion Au/electroless Ni solder joints after aging”, Materials Science and Engineering: B 177, 278 (2012).
 J. Y. Kim and Y. Jin, “Effects of residual impurities in electroplated Cu on the Kirkendall void formation during soldering”, Applied Physics Letters 92, 092109 (2008).
 J. Yu and J. Y. Kim, “Effects of residual S on Kirkendall void formation at Cu/Sn–3.5Ag solder joints”, Acta Materialia 56, 5514 (2008).
 Y. W. Wang, Y. W. Lin, and C. R. Kao, “Kirkendall voids formation in the reaction between Ni-doped SnAg lead-free solders and different Cu substrates”, Microelectronics Reliability 49, 248 (2009).
 Y. J. Chen, C. K. Chung, C. R. Yang, and C. R. Kao, “Single-joint shear strength of micro Cu pillar solder bumps with different amounts of intermetallics”, Microelectronics Reliability 53, 47 (2013).
 N. S. Bosco and F. W. Zok, “Critical interlayer thickness for transient liquid phase bonding in the Cu–Sn system”, Acta Materialia 52, 2965 (2004).
 Y. C. Chan, P. L. Tu, C. W. Tang, K. C. Hung, and J. K. L. Lai, “Reliability studies μBGA solder joints-effect of Ni-Sn intermetallic compound”, IEEE Transactions on Advanced Packaging 24, 25 (2001).
 H. Y. Chuang, W. M. Chen, W. L. Shih, Y. S. Lai, and C. R. Kao, “Critical new issues relating to interfacial reactions arising from low solder volume in 3D IC packaging”, Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, 1723 (2011).
 H. Y. Chuang, T. L. Yang, M. S. Kuo, Y. J. Chen, J. J. Yu, C. C. Li, and C. R. Kao, “Critical Concerns in Soldering Reactions Arising from Space Confinement in 3-D IC Packages”, Ieee Transactions on Device and Materials Reliability 12, 233 (2012).
 H. Y. Chuang, J. J. Yu, M. S. Kuo, H. M. Tong, and C. R. Kao, “Elimination of voids in reactions between Ni and Sn: A novel effect of silver”, Scripta Materialia 66, 171 (2012).
 C. C. Chuang, T. F. Yang, J. Y. Juang, Y. P. Hung, C. J. Zhan, Y. M. Lin, C. T. Lin, P. C. Chang, and T. C. Chang, “Influence of underfill materials on the reliability of coreless flip chip package”, Microelectronics Reliability 48, 1875 (2008).
 A. Hamada, T. Furusawa, N. Saito, and E. Takeda, “A new aspect of mechanical stress effects in scaled MOS devices”, Electron Devices, IEEE Transactions on 38, 895 (1991).
 S. Savastiouk, O. Siniaguine, and M. DiOrio, “Moore’s law the next dimension”, Adv. Packag. 7, 55 (1998).
 K. Takahashi, M. Umemoto, N. Tanaka, K. Tanida, Y. Nemoto, Y. Tomita, M. Tago, and M. Bonkohara, “Ultra-high-density interconnection technology of three-dimensional packaging”, Microelectronics Reliability 43, 1267 (2003).
 T. Alander, I. Suominen, P. Heino, and E. Ristolainen, “Improving the fatigue life of a bare die flip chip by thinning”, Soldering & Surface Mount Technology 15, 8 (2003).
 S. Katsurayama and H. Tohmyoh, “Effect of Warpage of Flip Chip Packages Due to the Underfill Encapsulating Process on Interconnect Reliability”, Journal of Electronic Packaging 131, 031005 (2009).
 K. Verma, D. Columbus, and B. Han, “Development of real time/variable sensitivity warpage measurement technique and its application to plastic ball grid array package”, Electronics Packaging Manufacturing, IEEE Transactions on 22, 63 (1999).
 J. Stopford, A. Henry, D. Manessis, N. Bennett, K. Horan, D. Allen, J. Wittge, L. Boettcher, A. Cowley, and P. J. McNally, “Non-destructive X-Ray mapping of strain & warpage of die in packaged chips”, Microelectronics and Packaging Conference (EMPC), 2011 18th European, 1 (2011).
 S. A. Gee, W. F. Van Den Bogert, and V. R. Akylas, “Strain-gauge mapping of die surface stresses”, Components, Hybrids, and Manufacturing Technology, IEEE Transactions on 12, 587 (1989).
 R. Darveaux, L. T. Hwang, A. Reisman, and I. Turlik, “Thermal stress analysis of a multichip package design”, Electronic Components Conference, 1989. Proceedings., 39th, 668 (1989).
 T. Akio and I. Nobuyuki, “Nondestructive Warpage Measurements of LSI Chips in a Stacked System in Package by Using High-Energy X-ray Diffraction”, Japanese Journal of Applied Physics 49, 04DB03 (2010).
 J. Kanatharana, J. J. Pérez-Camacho, T. Buckley, P. J. McNally, T. Tuomi, M. O. Hare, D. Lowney, W. Chen, R. Rantamäki, L. Knuuttila, and J. Riikonen, “Mapping of mechanical stresses in silicon substrates due to lead–tin solder bump reflow process via synchrotron x-ray topography and finite element modelling”, Journal of Physics D: Applied Physics 36, A60 (2003).
 P. J. McNally, J. Kanatharana, B. H. W. Toh, D. W. McNeill, A. N. Danilewsky, T. Tuomi, L. Knuuttila, J. Riikonen, J. Toivonen, and R. Simon, “Geometric linewidth and the impact of thermal processing on the stress regimes induced by electroless copper metallization for Si integrated circuit interconnect technology”, Journal of Applied Physics 96, 7596 (2004).
 A. T. Wu, C. Y. Tsai, C. L. Kao, M. K. Shih, Y. S. Lai, H. Y. Lee, and C. S. Ku, “In Situ Measurements of Thermal and Electrical Effects of Strain in Flip-Chip Silicon Dies Using Synchrotron Radiation X-rays”, Journal of Electronic Materials 38, 2308 (2009).
 A. T. Wu, K. N. Tu, J. R. Lloyd, N. Tamura, B. C. Valek, and C. R. Kao, “Electromigration-induced microstructure evolution in tin studied by synchrotron x-ray microdiffraction”, Applied Physics Letters 85, 2490 (2004).
 A. S. Budiman, S. M. Han, J. R. Greer, N. Tamura, J. R. Patel, and W. D. Nix, “A search for evidence of strain gradient hardening in Au submicron pillars under uniaxial compression using synchrotron X-ray microdiffraction”, Acta Materialia 56, 602 (2008).
 A. S. Budiman, G. Lee, M. J. Burek, D. Jang, S. M. J. Han, N. Tamura, M. Kunz, J. R. Greer, and T. Y. Tsui, “Plasticity of indium nanostructures as revealed by synchrotron X-ray microdiffraction”, Materials Science and Engineering: A 538, 89 (2012).
 A. S. Budiman, H. A. S. Shin, B. J. Kim, S. H. Hwang, H. Y. Son, M. S. Suh, Q. H. Chung, K. Y. Byun, N. Tamura, M. Kunz, and Y. C. Joo, “Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits”, Microelectronics Reliability 52, 530 (2012).
 G. Xu, F. Geng, Q. Huang, L. Luo, and J. Zhou, “Warpage and Reliability of a 3D-MCM on an Embedded Substrate With Multiple Interconnection Method”, IEEE Transactions on Components and Packaging Technologies 33, 571 (2010).
 B. Han, “Thermal stresses in microelectronics subassemblies: Quantitative characterization using photomechanics methods”, Journal of Thermal Stresses 26, 583 (2003).
 M. O. Alam and Y. C. Chan, “Solid-state growth kinetics of Ni3Sn4 at the Sn–3.5Ag solder∕Ni interface”, Journal of Applied Physics 98, 123527 (2005).
 M. He, Z. Chen, and G. Qi, “Solid state interfacial reaction of Sn–37Pb and Sn–3.5Ag solders with Ni–P under bump metallization”, Acta Materialia 52, 2047 (2004).
 X. Hu and Z. Ke, “Growth behavior of interfacial Cu–Sn intermetallic compounds of Sn/Cu reaction couples during dip soldering and aging”, Journal of Materials Science: Materials in Electronics 25, 936 (2014).
 C. P. Huang, C. Chen, C. Y. Liu, S. S. Lin, and K. H. Chen, “Metallurgical reactions of Sn-3.5Ag solder with various thicknesses of electroplated Ni/Cu under bump metallization”, Journal of Materials Research 20, 2772 (2005).
 S. Ishikawa, E. Hashino, T. Kono, and K. Tatsumi, “IMC Growth of Solid State Reaction between Ni UBM and Sn–3Ag–0.5Cu and Sn–3.5Ag Solder Bump Using Ball Place Bumping Method during Aging”, Materials Transactions 46, 2351 (2005).
 R. Labie, W. Ruythooren, and J. Van Humbeeck, “Solid state diffusion in Cu–Sn and Ni–Sn diffusion couples with flip-chip scale dimensions”, Intermetallics 15, 396 (2007).
 M. Mita, M. Kajihara, N. Kurokawa, and K. Sakamoto, “Growth behavior of Ni3Sn4 layer during reactive diffusion between Ni and Sn at solid-state temperatures”, Materials Science and Engineering: A 403, 269 (2005).
 N. Mookam and K. Kanlayasiri, “Evolution of Intermetallic Compounds between Sn-0.3Ag-0.7Cu Low-silver Lead-free Solder and Cu Substrate during Thermal Aging”, Journal of Materials Science & Technology 28, 53 (2012).
 J. Y. Song, J. Yu, and T. Y. Lee, “Analysis of Phase Transformation Kinetics by Intrinsic Stress Evolutions During the Isothermal Aging of Amorphous Ni(P) and Sn/Ni(P) Films”, Journal of Materials Research 19, 1257 (2011).
 C. K. Wong, J. H. L. Pang, J. W. Tew, B. K. Lok, H. J. Lu, F. L. Ng, and Y. F. Sun, “The influence of solder volume and pad area on Sn–3.8Ag–0.7Cu and Ni UBM reaction in reflow soldering and isothermal aging”, Microelectronics Reliability 48, 611 (2008).
 J. W. Yoon and S. B. Jung, “Growth kinetics of Ni3Sn4 and Ni3P layer between Sn–3.5Ag solder and electroless Ni–P substrate”, Journal of Alloys and Compounds 376, 105 (2004).
 J. W. Yoon, C. B. Lee, D. U. Kim, and S. B. Jung, “Reaction diffusions of Cu6Sn5 and Cu3Sn intermetallic compound in the couple of Sn-3.5Ag eutectic solder and copper substrate”, Metals and Materials International 9, 193 (2003).
 W. M. Tang, A. Q. He, Q. Liu, and D. G. Ivey, “Solid state interfacial reactions in electrodeposited Cu/Sn couples”, Transactions of Nonferrous Metals Society of China 20, 90 (2010).
 M. Yang, H. T. Chen, X. Ma, M. Y. Li, Y. Cao, and J. Kim, “Solid-state interfacial reaction of eutectic Sn3.5Ag and pure tin solders with polycrystalline Cu substrate”, Journal of Materials Science 49, 3652 (2014).
 R. W. Yang, Y. W. Chang, W. C. Sung, and C. Chen, “Precipitation of large Ag3Sn intermetallic compounds in Sn2.5Ag microbumps after multiple reflows in 3D-IC packaging”, Materials Chemistry and Physics 134, 340 (2012).
 H. Y. You, Y. C. Hwang, J. W. Pyun, Y. G. Ryu, and H. S. Kim, “Chip package interaction in micro bump and TSV structure”, Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, 315 (2012).
 S. L. Wright, C. K. Tsang, J. Maria, B. Dang, R. Polastre, P. Andry, and J. Knickerbocker, “Micro-interconnection reliability: Thermal, electrical and mechanical stress”, Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, 1278 (2012).
 M. L. Huang, T. Loeher, A. Ostmann, and H. Reichl, “Role of Cu in dissolution kinetics of Cu metallization in molten Sn-based solders”, Applied Physics Letters 86, 181908 (2005).
 V. I. Dybkov, “Effect of Dissolution on the Ni3Sn4 Growth Kinetics at the Interface of Ni and Liquid Sn-Base Solders”, Solid State Phenomena 138, 153 (2008).
 C. S. Liu and C. E. Ho, “Role of Ni and Cu metallization dissolution in various Ni/solder/Cu jointing sequences”, Microsystems Packaging Assembly and Circuits Technology Conference (IMPACT), 2010 5th International, 1 (2010).
 J. W. Yoon, B. I. Noh, and S. B. Jung, “Effects of third element and surface finish on interfacial reactions of Sn–Ag–xCu (or Ni)/(Cu or ENIG) solder joints”, Journal of Alloys and Compounds 506, 331 (2010).
 D. R. Frear, S. N. Burchett, H. S. Morgan, and J. H. Lau, “The Mechanics of Solder Alloy Interconnects (Van Nostrand Reinhold, New York)”, (1994).
 T. Eckert, O. Bochow-Ness, A. Middendorf, K. Tetzner, and H. Reichl, “Condition indicators for reliability monitoring of microsystems”, Electronics System-Integration Technology Conference, 2008. ESTC 2008. 2nd, 1035 (2008).
 T. Takahashi, S. Komatsu, H. Nishikawa, and T. Takemoto, “High-Temperature Resistant Intermetallic Compound Joints for Si Chips and Cu Substrates”, Journal of Electronic Materials 39, 2274 (2010).
 G. T. Galyon and L. Palmer, “An integrated theory of whisker formation: the physical metallurgy of whisker formation and the role of internal stresses”, Electronics Packaging Manufacturing, IEEE Transactions on 28, 17 (2005).
 J. H. Lau and S. W. Lee, “Effects of Underfill Delamination and Chip Size on the Reliability of Solder Bumped Flip Chip on Board”, The International Journal of Microcircuits and Electronic Packaging 23, 33 (2000).
 J. Cheng, S. Chen, P. T. Vianco, and J. C. M. Li, “Quantitative analysis for hillocks grown from electroplated Sn film”, Journal of Applied Physics 107, 074902 (2010).
 E. Chason, N. Jadhav, W. L. Chan, L. Reinbold, and K. S. Kumar, “Whisker formation in Sn and Pb–Sn coatings: Role of intermetallic growth, stress evolution, and plastic deformation processes”, Applied Physics Letters 92 (2008).
 S. Kim and J. Yu, “Recrystallization-induced void migration in electroplated Cu films”, Scripta Materialia 67, 312 (2012).
 K. N. Tu, C. Chen, and A. T. Wu, “Stress analysis of spontaneous Sn whisker growth” in “Lead-Free Electronic Solders” (Springer US, 2007), 269 (2007).
 Z. K. A. Jalar, R. Rasid, S. Abdullah, and N.K. and Othman, “The Effect of Underfill Fillet Geometry to Die Edge Stress for Flip Chip Packaging”, Advanced Materials Research 148, 1108 (2010).
 K. P. Wang, Y. Y. Huang, A. Chandra, and K. X. Hu, “Interfacial shear stress, peeling stress, and die cracking stress in trilayer electronic assemblies”, IEEE Transactions on Components and Packaging Technologies 23, 309 (2000).
 M. Modi, C. McCormick, and N. Armendariz, “New insights in critical solder joint location”, Electronic Components and Technology Conference, 2005. Proceedings. 55th, 977 (2005).
 T. Y. Tee, H. S. Ng, D. Yap, X. Baraton, and Z. Zhong, “Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications”, Microelectronics Reliability 43, 1117 (2003).