博碩士論文 985201020 詳細資訊




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姓名 范綱弈(Kang-Yi Fan)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 適用於3GPP-LTE系統高行車速率基頻接收機之設計
(The Design of Baseband Receiver for 3GPP-LTE System under High Mobility)
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摘要(中) 在下世代的行動通訊系統中,3GPP LTE/LTE-Advanced為目前世界上行動通訊的主要規格之一,主要採用正交分頻多工存取調變,對於高頻選擇性衰減通道有著較強的抵抗力。所以本論文以LTE的規格,並搭配多輸入多輸出技術,來實作接收機。
在接收機通能區塊上,大致可分為兩個部分。同步錯誤追蹤部分,使用2對參考訊號來估測殘餘的載波頻率偏移,另一部分為通道變化的追蹤,主要利用可適性RLS來追蹤時間方向內插器的係數。
在硬體設計上面,採用下列技術來降低硬體複雜度。利用排程將讀寫的時間錯開,減少記憶體使用的埠數,也可減少記憶體的使用量,來降低硬體消耗。在可適性RLS方面,運用排程來解決因為加入管線級暫存器而造成的係數更新問題,並設立係數更新機制,防止有限精度造成量化錯誤在遞迴過程累積使係數發散。
整個接收機在車速240 km/hr的環境下有良好的表現,我們更嘗試支援到360 km/hr,並加入多輸入多輸出來增加throughput。而整個接收機有透過FPGA做驗證,而通道追蹤的部分,更有透過CIC下線,做出晶片驗證。晶片大小2.46 × 2.46 mm2,使用CQFP144封裝,core gate count 1023K,最大頻率為100 MHz,throughtput最高達到497.75 Mbps。
摘要(英) LTE/LTE-Advance is one of the main standards for the next-generation mobile communication system. It uses OFDMA for modulation, which has better resistance to highly frequency-selective fading channels. In this thesis, a baseband receiver that follows the parameters of LTE/LTE-A and incorporates the MIMO conficuration is designed.
Two essential functional blocks are considered in the receiver. The first part is related with synchronization. Two pairs of reference signals are used to estimate the residual synchronization errors. The other part is designed for tracking channel variation under high mobility. It uses adaptive RLS algorithm to accelerate convergence of the filter coefficents.
As to the hardware design, we propose some techniques to reduce the complexity. The data-paths are well-scheduled so that non-comflict memory access can be accomplished with reduced memory I/O ports, and memory sizes. For the implementation of the adaptive RLS algorithm, the RLS updating procedureis also re-scheduled to solve the problem caused by insertion of pipeline registers. Furthermore, a novel reset mechanism is designed to prevent the divergence resulted from the quantization error accumulation due to finite precision effect in the iterative loops.
The receiver is verified to have satisfying performance under mobility of 240 km/hr, and even up to 360 km/hr. In the end, we verify the receiver on the FPGA platform. The block of channel tracking engine is taped out through CIC. The chip size is 2.46 × 2.46 mm2, and the pakage is CQFP144. The gate count is 1023K, and from post-layout simulation, the max frequency achieves 100 MHz, and the throughput is 497.75 Mbps.
關鍵字(中) ★ 3GPP-LTE
★ 高速
★ 基頻
★ 接收機
關鍵字(英) ★ 3GPP-LTE
★ receiver
★ baseband
★ high mobility
論文目次 目錄 III
表目錄 VI
圖目錄 VII
第1章 緒論 1
1.1 簡介與研究動機 1
1.2 論文組織 2
第2章 正交分頻多工存取(OFDMA)技術與3GPP LTE系統介紹 3
2.1 正交分頻多工存取調變技術介紹 3
2.1.1 正交分頻多工存取(OFDMA)調變技術 3
2.1.2 保護區間與循環前置介紹 7
2.2 3GPP LTE系統介紹 10
2.2.1 下行(Downlink)參數簡介 10
2.2.2 參考訊號(Reference Signal) 13
2.2.3 主要同步訊號(Primary Synchronization Signal) 16
第3章 基頻通道介紹 18
3.1 多重路徑衰減通道模型 19
3.2 加成性白高斯雜訊 21
3.3 載波頻率偏移 22
3.4 取樣時脈偏移 23
第4章 同步錯誤追蹤及通道變化追蹤與信號偵測 24
4.1 同步錯誤追蹤 25
4.1.1 符元邊界偵測 26
4.1.2 小數載波頻率偏移偵測 27
4.1.3 整數載波頻率偏移偵測 28
4.1.4 殘餘載波頻率偏移估測 29
4.2 高速通道變化追蹤 33
4.2.1 通道內插器 33
4.2.2 RLS通道追蹤演算法 36
4.2.3 純化通道頻率響應 39
4.3 載波間干擾效應與補償 43
4.4 系統效能模擬 46
第5章 硬體設計與實現 47
5.1 設計區塊圖 47
5.2 符元邊界偵測與小數載波頻率偏移偵測設計 50
5.3 整數部份載波頻率偏移偵測設計 52
5.4 殘餘部份載波頻率偏移偵測設計 53
5.5 資料緩衝記憶體與領航訊號儲存記憶體 55
5.6 領航訊號攫取緩衝記憶體設計 56
5.7 時間方向內插器設計 60
5.8 頻率方向內插器設計 62
5.9 多輸入多輸出訊號偵測器設計 63
5.10 載波間干擾消除設計 67
5.11 排序選擇性純化通道響應設計 73
5.12 可適性RLS演算法設計 75
5.12.1 排程改善 75
5.12.2 硬體電路架構 77
5.12.3 係數更新機制 82
5.13 系統效能模擬 84
第6章 實作成果 86
6.1 FPGA實作 86
6.2 晶片實作 91
6.2.1 晶片設計 91
6.2.2 晶片佈局結果與規格 94
6.2.3 晶片模擬結果比較 99
第7章 結論 101
參考資料 102
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[2] 3GPP TS 36.211 V8.3.0: Evolved Universal Terrestrial Radio Access (E-UTRA) Physical Channels and and Modulation, 2008.
[3] 3GPP TS 36.211 V10.5.0: Evolved Universal Terrestrial Radio Access (E-UTRA) Physical Channels and and Modulation, 2012.
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[6] Pei-Yun Tsai, Hsin-Yu Kang, and Tzi-Dar Chireh, "Joint Weighted Least Squares Estimation of Frequency and Timing Offset for OFDM Systems Over Fading Channels," the 57-th IEEE Semiannual VTC, 2003-spring, pp. 2543-2547.
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[16] SMIMS, VeriEnterprise VEX-V5 Hardware Reference Manual, 2009.
[17] Jung-Mao Lin, Hsin-Yi Yu, Yu-Jen Wu, and His-Pin Ma, "A Power Efficient Baseband Engine for Multiuser Mobile MIMO-OFDMA Communications," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 7, pp. 1779-1792, July 2010.
[18] Chia-Ching Lee, Chun-Fu Liao, Chao-Ming Chen, and Yuan-Hao Huang, "Design of 4x4 MIMO-OFDMA Receiver with Precode Codebook Search for 3GPP-LTE," IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 3957-3960.
[19] Ming-Fu Sun, Ta-Yang Juan, Kan-Si Lin, and Terng-Yin Hsu, "Adaptive Frequency-Domain Channel Estimator in 4x4 MIMO-OFDM Modems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 11, pp. 1616-1625, Nov. 2009.
[20] Gene C.H. Chuang et al., "A MIMO WiMAX SoC in 90nm CMOS for 300km/h Mobility," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011, pp. 134-136.
指導教授 蔡佩芸(Pei-Yun Tsai) 審核日期 2012-7-3
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