具正交相位輸出之低電壓操作同步複製延遲電路

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姓名

許智勛(Chih-hsun Hsu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具正交相位輸出之低電壓操作同步複製延遲電路
(A Low Supply Voltage Synchronous Mirror Delay with Quadrature Phase Output)

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摘要(中)

摘要
本論文提出一個具正交相位時脈輸出之低電壓操作同步複製延遲電路晶片設計。此
電路將在前3 個週期執行粗調動作，爾後的8 個週期完成細微調整，藉由兩階段的調整
達到時脈同步的功能。細微調整可以進一步降低同步時脈的靜態相位誤差，並且採用環
形動態調整機制，能夠讓時脈在同步後，仍能保有動態追鎖的校正功能。另外，透過兩
階段邊緣偵測器與正交可調延遲電路，重複利用延遲量測電路，提供了一個與同步時脈
訊號相差了90 度相位的正交相位輸出，建立一組I/Q 通道。本電路將可適用於低電壓
時脈同步與資料傳送的應用，如生醫訊號感測系統。因其採全數位低電壓操作進行設計，
並將可適用於單晶片系統設計。
本論文之同步複製延遲電路使用TSMC 90 nm 1P9M CMOS 製程實現晶片，電路
操作電壓為0.5 V，其操作頻率範圍可從220 MHz 到570 MHz，同步時脈間之相位誤
差≦100.5 ps，正交同步時脈間之相位誤差≦144.4 ps。在操作頻率為570 MHz 時，功
率消耗為1.95 mW。而內部時脈輸出訊號之最大峰對峰值時間抖動量為31.78 ps (1.81
%)，方均根抖動量為3.99 ps，正交相位輸出訊號之最大峰對峰值時間抖動量為34.67 ps
(1.97 %)，方均根抖動量為4.48 ps。整體晶片面積為517 × 594 um2，核心電路的面
積為188 × 171 um2。

摘要(英)

Abstract
A low supply voltage synchronous mirror delay circuit with quadrature phase
clock output is proposed. The coarse tune operation of this clock synchronous circuit
is accomplished in five cycles, and then the fine tune operation is also accomplished
in following eight cycles. Therefore, the clock signal is synchronized by the two step
operations. The fine tune operation not only can reduce the static clock phase error
but also can dynamic calibrate the synchronized clock by using a ring circuit. The two
step edge detector and the quadrature variable delay line are use in the proposed
SMD to generate a quadrature phase output, which is lagging from the synchronous
internal clock with a 90° phase shift. The quadrature phase output is useful for low
voltage clock synchronous and data transmission application, like biomedical signal
sensor network. The proposed SMD is using the all-digital circuit design and operating
at low supply voltage, thus it is suitable for system-on-chip (SoC) systems application.
The experimental chip was fabricated by TSMC 90 nm 1P9M CMOS process.
The chip is operating at 0.5 V supply voltage. The static phase error between
synchronous clocks is less than 100.5 ps, furthermore the static phase error between
quadrature clocks is less than 144.4 ps. The measurement results show that the
operation range is from 220 MHz to 570 MHz, and the power consumption is 1.95 mW
at 570 MHz. The peak-to-peak jitter and RMS jitter of internal clock are 31.78 ps and
3.99 ps at 570 MHz, respectively. The peak-to-peak jitter and RMS jitter of quadrature
internal clock are 34.67 ps and 4.48 ps at 570 MHz, respectively. The whole chip area
is 517 × 594 um2, and the core area is 188 × 171 um2
.

關鍵字(中)

★ 低電壓
★ 多相位輸出
★ 同步複製延遲電路
★ 時脈同步電路

關鍵字(英)

★ multiphase
★ clock synchronous circuit
★ synchronous mirror delay
★ low voltage

論文目次

摘要 .................................................................................................................. i
Abstract ................................................................................................................ ii
目錄 ..................................................................................................................... iii
圖目錄 .................................................................................................................. v
表目錄 ................................................................................................................ vii
第1 章緒論 ......................................................................................................... 1
1.1 研究動機與目的 ...................................................................................... 1
1.2 研究目的及其應用 ................................................................................... 3
1.3 論文架構 ................................................................................................. 3
第2 章同步複製延遲電路先前技術探討 .............................................................. 4
2.1 同步複製延遲電路 ................................................................................... 4
2.2 傳統式同步複製延遲電路[3] .................................................................... 5
2.3 插入式同步複製延遲電路[4] .................................................................... 8
2.4 減少面積的插入式同步複製延遲電路[5] .................................................. 9
2.5 直接誤差偵測同步複製延遲電路[6] ....................................................... 10
2.6 類比式同步複製延遲電路[7] .................................................................. 11
2.7 混合式同步複製延遲電路[8] .................................................................. 13
2.8 逐步近似暫存器同步複製延遲電路[9] .................................................... 14
2.9 任意責任週期之同步複製延遲電路[10] .................................................. 15
2.10 高精準度任意責任週期之同步複製延遲電路[1] ................................... 16
2.11 多相位輸出之同步複製延遲電路[11] .................................................... 17
2.12 總結 .................................................................................................... 18
第3 章具正交相位輸出之低電壓操作同步複製延遲電路 ................................... 19
3.1 設計概念 ............................................................................................... 19
3.2 具正交相位輸出之低電壓操作同步複製延遲電路架構與原理 ................ 20
3.3 粗調延遲電路 ........................................................................................ 22
iv
3.3.1 兩階段邊緣偵測器 ...................................................................... 24
3.3.2 量測延遲電路及改良複製控制電路 ............................................. 25
3.3.3 可調延遲電路 .............................................................................. 26
3.4 細調延遲電路 ........................................................................................ 27
3.4.1 相位偵測器 ................................................................................. 28
3.4.2 環形相位位移器 .......................................................................... 30
3.4.3 細調延遲路徑 .............................................................................. 32
3.5 正交相位輸出電路 ................................................................................. 34
3.5.1 正交可調延遲路徑控制電路 ........................................................ 35
3.5.2 正交可調延遲路徑 ...................................................................... 37
3.6 同步複製延遲電路於低電壓操作適應技巧 ............................................. 38
3.6.1 順向基體偏壓技巧 ...................................................................... 38
3.6.2 延伸型真單一相位時脈正反器(E-TSPC D-Flipflop) ..................... 40
第4 章電路模擬與晶片量測結果 ....................................................................... 42
4.1 設計流程 ............................................................................................... 42
4.2 佈局前電路模擬 .................................................................................... 42
4.3 電路佈局與佈局後電路模擬 .................................................................. 46
4.4 晶片照相與量測環境設定 ...................................................................... 52
4.5 量測結果 ............................................................................................... 54
4.6 規格比較 ............................................................................................... 61
第5 章結論與未來研究方向 .............................................................................. 62
5.1 結論 ...................................................................................................... 62
5.2 未來研究方向 ........................................................................................ 63
參考文獻 ............................................................................................................. 65

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指導教授

鄭國興(Kuo-hsing Cheng)

審核日期

2012-7-23

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