新穎奈米線穿隧式場效電晶體之技術開發

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姓名

李明師(Ming-Shih Lee) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

新穎奈米線穿隧式場效電晶體之技術開發
(Technology Development of Novel Naonwire Tunneling Field-Effect Transistor)

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摘要(中)

本論文整合一維複晶矽奈米線與PIN結構於一體，實作出奈米線穿隧式場效電晶體。期望能有效地改善金氧半場效電晶體的短通道效應、次臨限斜率與靜態漏電流。其關鍵製程簡述如下：利用側壁回蝕技術在陡直的平台側壁形成一維複晶矽奈米線，再藉由二次黃光微影製程分別對一維複晶矽奈米線進行P+ 和N+ 離子佈植形成PIN結構，進而實作出奈米線穿隧式場效電晶體。因此於變溫的電流-電壓曲線、次臨限斜率-溫度曲線以及導通電流-溫度曲線進行電性分析。

摘要(英)

This thesis integrated one dimension poly-Si nanowire and PIN structure into a device, which fabricated nanowire tunneling field-effect transistor (NWT-FET). We are looking forward to improving short channel effects (SCE), subthreshold slope, (S.S.) and static leakage current (IOFF) in the metal oxide semiconductor field-effect transistor (MOS-FET). The key process of NWT-FET is described as follows: By using etched back technique, we can form one dimension poly-Si nanowire on steep mesa-sidewall. Then by using two photolithography processes, we can implant P+ and N+ on one dimension poly-Si nanowire, respectively, to form the PIN structure. Via the variable temperature measurement (300 K, 250 K, 200 K and 150 K), we experimental characterized the current-voltage (I-V), subthreshold slope-temperature (S.S.-Temp.) and on current-temperature (Ion-Temp.).

關鍵字(中)

★ 奈米線
★ PIN
★ 奈米線穿隧式場效電晶體
★ 次臨限斜率
★ 靜態漏電流

關鍵字(英)

★ Nanowire
★ PIN
★ Nanowire Tunneling Field-Effect Transistor
★ Subthreshold Slope
★ Static Leakage Current

論文目次

中文摘要 I
英文摘要 II
誌謝 III
目錄 V
圖目錄 VII
表目錄 XI
一、緒論 1
1-1 研究的背景與動機 1
1-2 奈米線穿隧式場效電晶體的結構設計與製程考量 2
1-3 論文研究流程與架構 4
二、奈米線穿隧式場效電晶體的操作原理 9
2-1 前言 9
2-2 穿隧理論 9
2-3 元件結構與對應的能帶圖 11
2-4 操作機制 12
2-4-1 元件導通時對應的能帶圖 12
2-4-2 元件截止時對應的能帶圖 13
三、奈米線穿隧式場效電晶體製程開發與流程 17
3-1 前言 17
3-2 關鍵製程開發 17
3-3 元件製作流程 19
四、電性量測與分析 38
4-1 前言 38
4-2 奈米線穿隧式場效電晶體之常溫電性分析 38
4-3 奈米線穿隧式場效電晶體之變溫電性分析 41
五、總結與未來展望 49
參考文獻 50

參考文獻

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指導教授

李佩雯(Pei-Wen Li)

審核日期

2011-8-12

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