博碩士論文 985201061 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:9 、訪客IP:18.206.194.161
姓名 王靖雯(Ching-wen Wang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 以標準CMOS製程實現之850 nm矽光檢測器
(Photodetectors Fabricated by Standard CMOS Technology in 850 nm wavelength)
相關論文
★ 電子式基因序列偵測晶片之原型★ 增強型與空乏型砷化鋁鎵/砷化銦鎵假晶格高電子遷移率電晶體: 元件特性、模型與電路應用
★ 使用覆晶技術之微波與毫米波積體電路★ 注入增強型與電場終止型之絕緣閘雙極性電晶體佈局設計與分析
★ 600 V新型溝渠式載子儲存絕緣閘雙極性電晶體之設計★ 具有低摻雜P型緩衝層與穿透型P+射源結構之600V穿透式絕緣閘雙極性電晶體
★ 雙閘極金氧半場效電晶體與電路應用★ 空乏型功率金屬氧化物半導體場效電晶體 設計、模擬與特性分析
★ 高頻氮化鋁鎵/氮化鎵高速電子遷移率電晶體佈局設計及特性分析★ 氮化鎵電晶體 SPICE 模型建立 與反向導通特性分析
★ 加強型氮化鎵電晶體之閘極電流與電容研究和長時間測量分析★ 新型加強型氮化鎵高電子遷移率電晶體之電性探討
★ 離子佈植砷化鎵金屬半導體場效電晶體之研究★ 碰撞游離係數的量測及其在異質接面雙極性電晶體之設計應用
★ 磷化銦鎵/砷化鎵異質接面雙極性電晶體之研製及其集極調變對元件特性的影響★ 砷化鎵基體異質接面雙極性電晶體之研製與其在積體化功率放大器之應用
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 ( 永不開放)
摘要(中) 本論文利用0.18 ?m CMOS標準製程來實現矽光檢器,此光檢器主要由N/P-implant、N/P-well及Deep-N-Well所構成,其中Deep-N-Well另給偏壓的設計是為了排除大量基板慢速載子,此設計無論透過MEDICI二維元件模擬軟體亦或實際下線晶片的量測皆證明光檢測器頻寬的有效提升;其量測到的3-dB頻寬在元件同樣操作於N bias(反偏)為11.83 V情況下,可從未給DNW bias (即floating)時的200 MHz,提升至DNW bias為0 V時的2.69 GHz,同時其頻寬增益乘積為347.80 GHz,並且透過適當偏壓的調整可於N bias為11.50 V時達到最佳頻寬5.77 GHz。
而DNW另給偏壓的光檢測器架構雖能藉排除基板載子來提升頻寬,卻也因此使得響應度過低,如前述結構操作在最佳頻寬時5.77 GHz時,其響應度僅0.019 A/W。而本論文最後提出的結構即利用不同偏壓方式的設計,能有效收集在PD操作區中p-substrate照光產生的載子,明顯地提升了元件的響應度,其最佳的響應度於P bias為 -11.83 V時達到1.17 A/W,同時3-dB頻寬為1.9 GHz,達到較佳的頻寬與響應度乘積。
摘要(英) This work demonstrates photodetectors (PDs) fabricated by standard 0.18 ?m CMOS technology. In the proposed PD structure with Deep-N-Well layer, we show a obvious improvement when DNW bias is added. At reverse bias 11.83 V, the 3-dB bandwidth improve from 200 MHz to 2.69 GHz when the DNW bias vary from floating to 0 V. The reason may be the removal of slow diffusive carriers which are generated from substrate.
We also observe that the 3-dB bandwidth of our PDs will be better when the reverse bias get slightly decreased in the avalanche region. At reverse bias 11.50 V, the 3-dB bandwidth can achieve 5.77 GHz when DNW bias is 0 V. The possible reason may be the decrease of avalanche delay time. However, when we consider the speed and gain in the same time, the best bias condition is 11.83 V, which yield a gain-bandwidth product of 347.80 GHz.
Finally, a new photodetector with high responsivity has been demonstrated. The photodetector is biased by p-implant rather than n-implant in the previous design, and DNW layer is grounded with n-implant inside the PD. From both simulation and measurement result, the responsivity increase since the effective collection of hole generated inside the p-type susbrate in the operation region. The responsivity achieves 1.17 A/W, with 3-dB bandwidth of 1.9 GHz in the same time.
關鍵字(中) ★ 標準製程
★ 矽光檢測器
關鍵字(英) ★ CMOS process
★ si photodetector
論文目次 摘要 IV
Abstract V
致謝 VI
圖目錄 IX
表目錄 XIV
第一章 導論 1
1.1 動機 1
1.2 論文架構 2
第二章 光檢測器簡介 4
2.1 簡介 4
2.2 光纖通訊簡介 4
2.3 光檢測器簡介及其工作原理 7
2.4 光檢測器響應時間分析 10
2.5 以商用製程實現矽光檢測器 11
2.6 結論 19
第三章 標準CMOS製程之光檢測器 20
3.1 簡介 20
3.2 光檢測器MEDICI二維元件模擬及設計 20
3.3 元件響應度與頻率響應之量測 30
3.3.1 元件直流特性與響應度 30
3.3.2 元件頻率響應之測量 35
3.4 光檢測器於變溫條件下之直流特性量測 40
3.5 光檢測器模型萃取 50
3.6 結論 56
第四章 不同結構之光檢測器分析與比較 57
4.1 簡介 57
4.2 不同p-implant尺寸光檢測器之MEDICI二維元件模擬與設計 57
4.3 光檢測器響應度與頻率響應之測量 69
4.3.1 光檢測器直流特性與響應度 69
4.3.2 光檢測器頻率響應量測 75
4.4 光檢測器C-V特性量測 79
4.5 光檢測器模型萃取 83
4.6 結論 86
第五章 標準CMOS製程光檢測器之響應度改善 90
5.1 簡介 90
5.2 不同偏壓方式光檢測器之MEDICI二維元件模擬 90
5.3 元件響應度及頻率響應測量 97
5.3.1 元件直流特性與響應度量測 97
5.3.2 元件頻率響應量測 99
5.4 結論 100
第六章 總結 102
參考文獻 104
附錄A Edge-coupled PD MEDICI二維元件模擬與設計 106
附錄B 口試問題回答 114
參考文獻 [1] H. J. R. Dutton, "Understanding Optical Communications," Sep. 1998.
[2] S. O. Kasap, Optoelectronics and Photonics: Principles and Practices: Prentice Hall, 2001.
[3] G. P. Agrawal, "Fiber-Optical Communication Systems," 1997.
[4] F. Tavernier and M. S. J. Steyaert, "High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS," IEEE Journal of Solid-State Circuits , vol. 44, no.10, pp. 2856-2867, Oct. 2009.
[5] J. W. Shi, Slide of Ultra-High Speed Optoelectronic Devices, Chapter 4, 2006.
[6] C. Hermans and M. S. J. Steyaert, "A high-speed 850-nm optical receiver front-end in 0.18-mm CMOS," IEEE Journal of Solid-State Circuits, , vol. 41, no. 7 , pp. 1606-1614, Jul. 2006.
[7] S. Radovanovic, et al., "Physical and electrical bandwidths of integrated photodiodes in standard CMOS technology," IEEE Conference on Electron Devices and Solid-State Circuits 2003, pp. 95-98.
[8] W. K. Huang, et al., "Bandwidth enhancement in Si photodiode by eliminating slow diffusion photocarriers," Electronics Letters, vol. 44, no. 1, pp. 52-53, Jan. 2008.
[9] New Focus application notes No.1, "Insights into High-Speed Detectors and High-Frequency Techniques."
[10] S. Radovanovic, "High-Speed Photodiodes in Standard CMOS Technology," 2004.
[11] S. Radovanovic, et al., "A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication," IEEE Journal of Solid-State Circuits, vol. 40, no.8, pp. 1706-1717, Aug. 2005.
[12] B. Yang, et al., "10-Gb/s all-silicon optical receiver," IEEE Photonics Technology Letters, vol. 15, no.5, pp. 745-747, May 2003.
[13] S. G. Thomas, et al., "CMOS-compatible photodetector fabricated on thick SOI having deep implanted electrodes," Electronics Letters, vol. 38, no. 20, pp. 1202-1204,Sep. 2002.
[14] K. Iiyama, et al., "Hole-Injection-Type and Electron-Injection-Type Silicon Avalanche Photodiodes Fabricated by Standard 0.18 mm CMOS Process," IEEE Photonics Technology Letters, vol. 22, no. 12, pp. 932-934, Jun. 2010.
[15] M. J. Lee and W. Y. Choi, "A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain-bandwidth product," OPTICS EXPRESS, vol. 18, Nov. 2010.
[16] L. Dongmyung, et al., "An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer," IEEE Journal of Solid-State Circuits , vol. 45, no. 12, pp. 2861-2873, Dec. 2010.
[17] R. Fujimoto, et al., "A 7-GHz 1.8-dB NF CMOS low-noise amplifier," IEEE Journal of Solid-State Circuits, vol. 37, no.7, pp. 852-856, Jul. 2002.
[18] S. M. SZE and K. K. Ng, Physics of Semiconductor Devices, 3 ed.: John Wiley & Sons Inc, 2007.
[19] B. Kjornrattanawanich, et al., "Temperature dependence of the EUV responsivity of silicon photodiode detectors," IEEE Transactions on Electron Devices, vol. 53, no. 2, pp. 218-223, Feb. 2006.
[20] B. Ciftcioglu, et al., "Integrated Silicon PIN Photodiodes Using Deep N-Well
in a Standard 0.18-mm CMOS Technology," IEEE Journal of Lightwave
Technology, vol. 27,no. 15, pp. 3303-3313, Aug. 2009
[21] Y. Jin-Sung, et al., "High-Speed CMOS Integrated Optical Receiver With an
Avalanche Photodetector," IEEE Photonics Technology Letters, vol. 21,
no.20, pp. 1553-1555, 2009
指導教授 辛裕明(Yue-ming Hsin) 審核日期 2011-7-26
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明