砷化銦/銻化鋁高電子遷移率場效電晶體之次微米元件製程改善與元件衰化機構分析

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姓名

劉弘凱(Hong-Kai Liu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

砷化銦/銻化鋁高電子遷移率場效電晶體之次微米元件製程改善與元件衰化機構分析
(Development of Submicron Device Processes and Analysis of Device Degradation Mechanisms for InAs/AlSb HEMTs)

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摘要(中)

本論文利用砷化銦材料優異的高電子遷移率及優異電子飽和速度特性，發展次微米電子束微影閘極之低功率高速的異質接面場效電晶體(HFET)。我們也發展了可將汲極與源極的距離縮小的製程。我們觀察到銻化物元件隨著擺放時間的拉長產生了衰化的現象，針對此衰化現象我們也進行了研究。
我們利用改變光阻及控制顯影時間的方式，已可將汲極與源極之距離縮小至1μm。T型閘極長度0.2μm，汲極與源極的距離為1.5μm的元件特性於汲極偏壓VDS=0.4V下，其汲極飽和電流為IDSS=733mA/mm及轉導增益為gm=1,520mS/mm，電流增益截止頻率fT=105GHz。在研究元件衰化現象方面，我們觀察到了和剛製作完成的元件性能相比，元件在經過六個月後的出現了飽和電流增加、轉導增益上升、閘極漏電流變小、以及次臨限電壓位移的現象。我們利用了脈波電流-電壓量測(Pulse-IV)、X光能量色散分析儀(Energy-Dispersive Analysis with X-ray, EDAX)以及小訊號模型來進行分析，發現了元件在經過六個月後，磊晶會和大氣的氧元素發生反應，造成元件的衰化。

摘要(英)

We successfully developed low-power and high-speed e-beam submicron gate InAs-channel heterpjunction field-effect transistors in the thesis. A device process flow which includes source-to-drain spacing reduction and e-beam submicron T-gate lithography process was developed. Device degradation mechanism was also studied.
The spacing between source and drain can be decreased to 0.6μm by controlling development and baking times. In a HEMT device with a gate length of 0.2μm and a source-to-drain spacing of 1.5μm, IDSS=733mA/mm, gm=1520mS/mm, and the cut-off frequency fT=105GHz at the VDS=0.4V were obtained. Comparing device performance obtained at different times after device fabrication, we found that IDSS and gm increased, IG decreased, and Vth decreased with time. Pulsed I-V, EDAX, and small-signal model analysis suggested that the degradation behavior was very possibly due to the epitaxial oxidation in surface layers.

關鍵字(中)

★ 銻化鋁
★ 衰化
★ 砷化銦
★ 高電子遷移率電晶體

關鍵字(英)

★ AlSb
★ InAs
★ HEMT
★ degradation

論文目次

摘要 I
Abstract II
誌謝 III
圖目錄 VII
表目錄 XIII
第一章導論 1
1-1 砷化銦/銻化鋁之高速電子遷移率電晶體發展現況 1
1-2 銻化物元件衰化現象之研究現況 7
1-3 論文架構 8
第二章磊晶結構設計與次微米元件製程發展 10
2-1 前言 10
2-2 磊晶結構設計與材料分析 10
2.2.1 InAs/In0.5Al0.5As保護層磊晶結構(磊晶481) 10
2.2.2 InAs/In0.5Al0.5As保護層磊晶結構(磊晶650) 13
2.2.3 InAs/In0.5Al0.5As保護層磊晶結構(磊晶766) 20
2.2.4 InAs/In0.45Al0.55As保護層磊晶結構(磊晶767) 23
2.2.5 In0.2Al0.8Sb阻障層，InAs/In0.7Al0.3As保護層磊晶結構(磊晶730) 26
2.2.6 In0.2Al0.8Sb阻障層，InAs保護層磊晶結構(磊晶738) 29
2-3 次微米元件之製程發展 32
2.3.1 歐姆接觸製程發展 32
2.3.2 次微米T型閘極製程的發展 35
2-4 次微米元件之製程發展 39
2.4.1 標準次微米T型閘極元件製作 39
2.4.2 覆蓋鈍化層製程之次微米T型閘極製作流程 41
2-5 結論 44
第三章砷化銦/銻化鋁HFET之次微米元件特性 45
3-1 前言 45
3-2 InAs/In0.5Al0.5As覆蓋層之次微米元件性能 45
3.2.1 製程前覆蓋鈍化層元件 45
3.2.2 製程前不覆蓋鈍化層之次微米元件 54
3-3 不同磊晶保護層之元件性能 64
3.3.1 InAs/In0.5Al0.5As保護層磊晶結構(磊晶686) 64
3.3.2 InAs/In0.5Al0.5As保護層磊晶結構(磊晶766) 65
3.3.3 InAs/In0.45Al0.55As保護層磊晶結構(磊晶767) 67
3-4 銻化銦鋁阻障層之元件性能 69
3.4.1 In0.2Al0.8Sb阻障層，InAs/In0.7Al0.3As保護層磊晶結構(磊晶730) 69
3.4.2 In0.2Al0.8Sb阻障層，InAs保護層磊晶結構(磊晶738) 70
3-5 結論 72
第四章討論 73
4-1 前言 73
4-2 銻化物元件衰化現象之分析 73
4.2.1 銻化物元件衰化現象之電性變化 73
4.2.2 銻化物元件衰化現象之行為分析 75
4.2.3 結論 89
4-3 銻化鋁阻障層替換為銻化銦鋁之元件特性分析 90
4-4 結論 94
第五章結論與未來發展 95
結論： 95
未來發展： 96
參考文獻 97
附錄1不覆蓋鈍化層之元件製作流程 100
附錄2兩階段覆蓋鈍化層之元件製作流程 104
附錄3閘極後覆蓋鈍化層之元件製作流程 109
附錄4次微米閘極製作流程 113

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指導教授

蔡曜聰、林恒光
(Yao-Tsung Tsai、Heng-Kuang Lin)

審核日期

2011-9-22

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