博碩士論文 985201109 詳細資訊




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姓名 張藝儒(Yi-ju Chang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於大容量隨機存取記憶體之內建備份元件分析技術
(Built-In Redundancy-Analysis Schemes for Large-Capacity RAMs)
相關論文
★ 應用於三元內容定址記憶體之低功率設計與測試技術★ 用於隨機存取記憶體的接線驗證演算法
★ 用於降低系統晶片內測試資料之基礎矽智產★ 內容定址記憶體之鄰近區域樣型敏感瑕疵測試演算法
★ 內嵌式記憶體中位址及資料匯流排之串音瑕疵測試★ 用於系統晶片中單埠與多埠記憶體之自我修復技術
★ 用於修復嵌入式記憶體之基礎矽智產★ 自我修復記憶體之備份分析評估與驗證平台
★ 使用雙倍疊乘累加命中線之低功率三元內容定址記憶體設計★ 可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計
★ 低功率與可自我修復之三元內容定址記憶體設計★ 多核心系統晶片之診斷方法
★ 應用於網路晶片上隨機存取記憶體測試及修復之基礎矽智產★ 應用於貪睡靜態記憶體之有效診斷與修復技術
★ 應用於內嵌式記憶體之高效率診斷性資料壓縮與可測性方案★ 應用於隨機存取記憶體之有效良率及可靠度提升技術
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摘要(中) 在現今複雜的系統晶片(SOC)中,嵌入式記憶體是一個很重要之元件。這些系統晶片通常包含了大量的記憶體,而這些記憶體一般佔據整體系統晶片一半以上的面積,這造成記憶體良率會支配整體系統晶片之良率。因此,有效提升系統晶片中記憶體良率之技術是必須的。而記憶體內建自我修復技術(BISR)是一個已被廣泛使用於改善記憶體良率的有效技術。
一個BISR 電路通常包含一個內建備份元件分析(BIRA)電路來分配記憶體的備份元件,而BIRA 電路的效率好壞會很嚴重地影響BISR 的修復效率。論文的第一部分,針對擁有3D備份元件的大容量記憶體,提出了內建備份元件分析技術。這個技術提供了可程式化的功能,可以服務多個記憶體和支援多次測試的功能,使得可以進一步提升修復效率。實驗結果證明了這項技術可以達到很高的修復效率,針對128K-bit的記憶體,所提出的內建備份元件分析電路的面積負擔只為2.83%。
論文的第二部分,針對擁有3D 備份元件的大容量記憶體,提出了二個可以達到最佳修復效率的BIRA 技術。其中第一項技術使用了一個分析器就可以支援多個修復策略和支援字組導向記憶體執行同速測試與修復。由實驗結果觀察可知,這項技術是低面積負擔。舉例來說,針對2M-bit的記憶體有16個bank,且每個bank的大小為8192x16-bit,這個電路的面積負擔大約是0.92%。另外,為了去進一步減少面積成本,提出了一個低成本的內建備份元件分析技術,同樣可以使用一個分析器就可以支援多個修復策略,並且降低電路的面積成本,但是無法執行記憶體同速測試與修復。由實驗結果觀察可知,針對相同之記憶體,所提低成本的BIRA 電路的面積負擔大約只有0.62%。
摘要(英) In modern complex system-on-chip (SOC) designs, embedded random access memory (RAM)is a key component. A complex SOC typically contains a large number of RAM cores, and these cores usually occupy more than one half of the area of the SOC. Therefore, the yield of the SOC is dominated by the yield of RAM cores. Thus, effective yield-enhancement techniques are essential for RAM cores in SOCs. Built-in self-repair (BISR) technique has been acknowledged as one effective technique for improving the yield of embedded RAMs with redundancy.
A BISR circuit typically has a built-in redundancy-analysis (BIRA) module for allocating the redundancy. The efficiency of BIRA has heavy impact on the repair efficiency of the BISR circuit. In the first part of this thesis, we present a BIRA scheme for large RAMs with 3D redundancy (i.e., spare rows, spare columns, and spare IOs). The proposed BIRA scheme also can be designed as programmable such that it can serve multiple RAMs and support the multiple-time repair function to increase the repair rate further. Experimental results show that the proposed BISR scheme can achieve high repair rate and the area overhead of the proposed BIRA circuit for a 128K-bit RAM is only 2.83%.
In the second part of this thesis, two BIRA schemes with optimal repair rate for RAMs with 3D redundancy are proposed. One BIRA scheme using one analyzer to support multiple repair solutions is proposed to support the at-speed test and repair of word-oriented RAMs. Simulation results show that the area overhead of the proposed BIRA scheme is low. For example, the hardware overhead of the proposed BIRA circuit is about 0.92% for a 2M-bit RAM with sixteen 8192×16-bit banks. To reduce the area cost further, a low-cost parallel BIRA design using one analyzer to support multiple repair solutions is proposed as well to reduce the area cost of the BIRA circuit, but it cannot perform the test and repair of RAMs at speed. Simulation results show that the low-cost BIRA scheme can reduce the hardware overhead of the proposed BIRA circuit to about 0.62% for a 2M-bit RAM with sixteen 8192×16-bit banks.
關鍵字(中) ★ 記憶體修復
★ 記憶體測試
關鍵字(英) ★ memory repair
★ memory test
★ redundancy
★ yield enhancement
論文目次 1 Introduction 1
1.1 Memory Built-In Self-Repair Techniques . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Built-In Self-Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.2 Built-In Redundancy-Analysis Circuit . . . . . . . . . . . . . . . . . . 4
1.2 Existing BISR Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Thesis Motivations and Contributions . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 A BIRA Scheme for RAMs with 3D Redundancy 14
2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Targeted 3D Redundancy Architecture . . . . . . . . . . . . . . . . . . . . . 15
2.3 Proposed BIRA Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1 Proposed BIRA Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.2 Design for Programmability . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.3 BIRA Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Experimental Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.1 Repair Rate Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.2 Hardware Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3 BIRA Schemes with Optimal Repair Rate for RAMs with 3D Redundancy 32
3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.1 Challenges of BIRA Scheme with Optimal Repair Rate . . . . . . . . 33
3.1.2 Challenges of BIRA Scheme with Low Area Cost . . . . . . . . . . . 34
3.2 A BIRA Scheme with At-Speed Repair for Word-Oriented Memories . . . . . 35
3.2.1 Exhaustive Search Algorithm for Allocating 3D Redundancy . . . . . 35
3.2.2 Proposed BIRA Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.3 Shared Parallel BIRA . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.4 Design of the Proposed At-Speed BIRA Circuit . . . . . . . . . . . . 45
3.2.5 Problem of the At-Speed BIRA for RAMs with 3D Redundancy . . . 51
3.3 A BIRA Scheme with Low Area Cost for Word-Oriented Memories . . . . . 52
3.3.1 Proposed BIRA Scheme . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3.2 Low-Cost Parallel BIRA . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3.3 Design of the BIRA Circuit . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.4 Design of the BIRA with the Best Efficiency . . . . . . . . . . . . . . 59
3.4 Experimental Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.1 Area Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.2 Area Cost Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4 Comparisons of the Heuristic and Exhaustive BIRA Schemes 72
4.1 Repair Rate Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2 Hardware Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3 Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5 Conclusions and Future Work 78
5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
參考文獻 [1] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self-repair analyzer (CRESTA) for embedded DRAMs,” in Proc. Int’l Test Conf. (ITC), 2000, pp. 567–574.
[2] P. Ohler, S. Hellebrand, and H.-J. Wunderlich, “An integrated built-in test and repair approach for memories with 2D redundancy,” in IEEE European Test Symposium (ETS), Freiburg, May 2007, pp. 91–96.
[3] S. Hamdioui, G. Gaydadjiev, and A. van de Goor, “The state-of-art and future trends in testing embedded memories,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2004, pp. 54–59.
[4] M. Nicolaidis, N. Achouri, and L. Anghel, “A diversified memory built-in self-repair approach for nanotechnologies,” in Proc. IEEE VLSI Test Symp. (VTS), Napa Valley, Apr. 2004, pp. 313–318.
[5] R. C. Aitken, “Applying defect-based test to embedded memories in a COT model,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), San Jose, July 2003, pp. 72–77.
[6] Y. Zorian and S. Shoukourian, “Embedded-memory test and repair: Infrastructure IP for SoC yield,” IEEE Design & Test of Computers, vol. 20, no. 3, pp. 58–66, May-June 2003.
[7] M. Nicolaidis, N. Achouri, and S. Boutobza, “Optimal reconfiguration functions for column or data-bit built-in self-repair,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), Munich, Mar. 2003, pp. 590–595.
[8] C.-L. Su, Y.-T. Yeh, and C.-W.Wu, “An integrated ECC and redundancy repair scheme for memory reliability enhancement,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Monterey, CA, Oct. 2005, pp. 81–89.
[9] A. Benso, S. Chiusano, G. Di Natale, and P. Prinetto, “An on-line BIST RAM architecture with self-repair capabilities,” IEEE Trans. on Reliability, vol. 51, no. 1, pp. 123–128, Mar. 2002.
[10] A. Tanabe, T. Takeshima, H. Koike, Y. Aimoto, M. Takada, T. Ishijima, N. Kasai, H. Hada, K. Shibahara, T. Kunio, T. Tanigawa, T. Saeki, M. Sakao, H. Miyamoto, H. Nozue, S. Ohya, T. Murotani, K. Koyama, and T. Okuda, “A 30-ns 64-Mb DRAM with built-in self-test and self-repair function,” IEEE Jour. of Solid-State Circuits, vol. 27, no. 11, pp. 1525–1533, Nov. 1992.
[11] P. Mazumder and Y.-S. Jih, “A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 1, pp. 124–136, Jan. 1993.
[12] O. Wada, T. Namekawa, H. Ito, A. Nakayama, and S. Fujii, “Post-packaging auto repair techniques for fast row cycle embedded DRAM,” in Proc. Int’l Test Conf. (ITC), Oct. 2004, pp. 1016–1023.
[13] M. Nicolaidis, N. Achouri, and L. Anghel, “A memory built-in self-repair for high defect densities based on error polarities,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Nov. 2003, pp. 459–466.
[14] I. Kang, W. Jeong, and S. Kang, “High-efficiency memory BISR with two serial RA stages using spare memories,” Electronics Letters, vol. 44, no. 8, pp. 515–517, Oct. 2008.
[15] H.-N. Liu, Y.-J. Huang, and J.-F. Li, “A built-in self-repair method for RAMs in meshbased NoCs,” in Proc. Int’l Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2009, pp. 259–262.
[16] Z.-Y.Wang, Y.-M. Tsai, and S.-K. Lu, “Built-in self-repair techniques for heterogeneous memory cores,” in IEEE Int’l Symp. on Dependable Computing, Nov. 2009, pp. 69–74.
[17] M. Rab, A. Bawa, and N. Touba, “Improving memory repair by selective row partitioning,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Oct. 2009, pp. 211–219.
[18] T.-W. Tseng, J.-F. Li, and C.-C. Hsu, “ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs,” IEEE Trans. on VLSI Systems, vol. 18, no. 6, pp. 921–932, June 2010.
[19] V. Schober, S. Paul, and O. Picot, “Memory built-in self-repair using redundant words,” in Proc. Int’l Test Conf. (ITC), 2001, pp. 995–1001.
[20] C.-L. Su, R.-F. Huang, and C.-W. Wu, “A processor-based built-in self-repair design for embedded memories,” in Proc. 12th IEEE Asian Test Symp. (ATS), Xian, Nov. 2003, pp. 366–371.
[21] I. Kim, Y. Zorian, G. Komoriya, H. Pham, F. P. Higgins, and J. L. Lewandowski, “Built in self repair for embedded high density SRAM,” in Proc. Int’l Test Conf. (ITC), 1998, pp. 1112–1119.
[22] R. Rajsuman, “Design and test of large embedded memories: an overview,” IEEE Design & Test of Computers, vol. 18, no. 3, pp. 16–27, May 2001.
[23] Y. Zorian, “Embedded memory test & repair: infrastructure IP for SOC yield,” in Proc. Int’l Test Conf. (ITC), 2002, pp. 340–349.
[24] S. Nakahara, K. Higeta, M. Kohno, T. Kawamura, and K. Kakitani, “Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm,”
in Proc. Int’l Test Conf. (ITC), 1999, pp. 301–310.
[25] D. K. Bhavsar, “An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264,” in Proc. Int’l Test Conf. (ITC), Atlantic City, Sept. 1999, pp. 311–318.
[26] D. Xiaogang, S. M. Reddy, W.-T. Cheng, J. Rayhawk, and N. Mukherjee, “At-speed built-in self-repair analyzer for embedded word-oriented memories,” in International Conference on VLSI Design, 2004, pp. 895–900.
[27] M. Nicolaidis, N. Achouri, and S. Boutobza, “Dynamic data-bit memory built-in selfrepair,” in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2003, pp. 588–594.
[28] S.-K. Lu, Y.-C. Tsai, C.-H. Hsu, K.-H. Wang, and C.-W. Wu, “Efficient built-in redundancy analysis for embedded memories with 2-D redundancy,” IEEE Trans. on VLSI Systems, vol. 14, no. 1, pp. 34–42, Jan. 2006.
[29] J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, “A built-in self-repair design for RAMs with 2-D redundancy,” IEEE Trans. on VLSI Systems, vol. 13, no. 6, pp. 742–745, June 2005.
[30] T.-W. Tseng, J.-F. Li, C.-C. Hsu, A. Pao, K. Chiu, and E. Chen, “A reconfigurable built-in self-repair scheme for multiple repairable RAMs in SOCs,” in Proc. Int’l Test Conf. (ITC), Oct. 2006, pp. 1–8.
[31] T.-W. Tseng, C.-H. Wu, Y.-J. Huang, J.-F. Li, A. Pao, K. Chiu, and E. Chen, “A built-in self-repair scheme for multiport RAMs,” in Proc. IEEE VLSI Test Symp. (VTS), May 2007, pp. 355–360.
[32] C.-D. Huang, J.-F. Li, and T.-W. Tseng, “ProTaR: an infrastructure IP for repairing RAMs in SOCs,” IEEE Trans. on VLSI Systems, vol. 15, no. 10, pp. 1135–1143, Oct. 2007.
[33] T.-W. Tseng and J.-F. Li, “A shared parallel built-in self-repair scheme for random access memories in SOCs,” in Proc. Int’l Test Conf. (ITC), Santa Clara, Oct. 2008, pp. 1–9.
[34] S. K. Thakur, R. A. Parekhji, and A. N. Chandorkar, “On-chip test and repair of memories for static and dynamic faults,” in Proc. Int’l Test Conf. (ITC), Oct. 2006, pp. 1–10.
[35] W. Jeong, I. Kang, K. Jin, and S. Kang, “A fast built-in redundancy analysis for memories with optimal repair rate using a line-based search tree,” IEEE Trans. on VLSI Systems, vol. 17, no. 12, pp. 1665–1678, Dec. 2009.
[36] S.-K. Lu, C.-L. Yang, Y.-C. Hsiao, and C.-W. Wu, “Efficient BISR techniques for embbedded memories considering cluster faults,” IEEE Trans. on VLSI Systems, vol. 18, no. 2, pp. 184–193, Feb. 2010.
[37] T.-W. Tseng, J.-F. Li, and C.-S. Hou, “A built-in method to repair SoC RAMs in parallel,” IEEE Design & Test of Computers, vol. 27, no. 6, pp. 46–57, Nov./Dec. 2010.
[38] J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, “A built-in self-repair scheme for semiconductor memories with 2-D redundancy,” in Proc. Int’l Test Conf. (ITC), Oct. 2003, pp. 393–402.
[39] S.-Y. Kuo and W. K. Fuchs, “Efficient spare allocation in reconfigurable arrays,” IEEE Design & Test of Computers, vol. 4, no. 1, pp. 24–31, Feb. 1987.
[40] J. R. Day, “A fault-driven, comprehensive redundancy algorithm,” IEEE Design & Test of Computers, vol. 2, no. 3, pp. 35–44, June 1985.
[41] C.-L. Wey and F. Lombardi, “On the repair of redundancy RAM’s,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, no. 2, pp. 222–231, March 1987.
[42] W.-K. Huang, Y.-N. Shen, and F. Lombardi, “New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement,” IEEE Trans. on
Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 3, pp. 323–328, Mar. 1990.
[43] T.-W. Tseng and J.-F. Li, “A low-cost built-in redundancy-analysis scheme for wordoriented RAMs with 2-D redundancy,” IEEE Trans. on VLSI Systems, July 2010 (accepted).
[44] T.-W. Tseng, J.-F. Li, and D.-M. Chang, “A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), Mar. 2006, pp. 53–58.
[45] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in redundancy analysis for memory yield improvement,” IEEE Trans. on Reliability, vol. 52, no. 4, pp. 386–399, Dec. 2003.
[46] T.-W. Tseng, Y.-J. Huang, and J.-F. Li, “DABISR: A defect-aware built-in self-repair scheme for single/multi-port RAMs in SOCs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 10, pp. 1628–1639, Oct. 2010.
[47] J.-F. Li, T.-W. Tseng, and C.-S. Hou, “Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faults,” IEEE Trans. on VLSI Systems, vol. 18, no. 9, pp. 1361–1366, Sept. 2010.
[48] S.-K. Lu and S.-C. Huang, “Built-in self-test and repair (BISTR) technique for embedded RAMs,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), 2004, pp. 60–64.
[49] K. Chakraborty, S. Kulkami, M. Bhattacharya, P. Mazumder, and A. Gupta, “A physical design tool for built-in self-repairable RAMs,” IEEE Trans. on VLSI Systems, vol. 9, no. 2, pp. 352–364, April 2001.
[50] S.-K. Lu and C.-H. Hsu, “Built-in self-repair for divided word line memory,” in Proc. IEEE Int’l Symp. on Circuits and Systems (ISCAS), 2001, pp. 13–16.
[51] M. Nicolaidis, N. Achouri, and L. Anghel, “Memory built-in self-repair for nanotechnologies,” in Proc. IEEE Int’l symp. on On-Line Testing (IOLTS), July 2003, pp. 94–98.
[52] K. Pekmestzi, N. Axelos, I. Sideris, and N. Moshopoulos, “A BISR architecture for embedded memories,” in Proc. IEEE Int’l symp. on On-Line Testing (IOLTS), July 2008, pp. 149–154.
[53] A. Sehgal, A. Dubey, E. Marinissen, C. Wouters, H. Vranken, and K. Chakrabarty, “Yield analysis for repairable embedded memories,” in Proc. IEEE European Test Workship (ETW), May 2003, pp. 35–40.
[54] S.-K. Lu, Y.-C. Tsai, and S.-C. Huang, “A BIRA algorithm for embedded memories with 2D redundancy,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2005, pp. 121–126.
[55] D.-M. Chang, J.-F. Li, and Y.-J. Huang, “A built-in redundancy-analysis scheme for random access memories with two-level redundancy,” Jour. of Electronic Testing: Theory and Applications, vol. 24, no. 1, pp. 181–192, Jan. 2008.
[56] S.-K. Lu, C.-L. Yang, and H.-W. Lin, “Efficient BISR techniques for word-oriented embedded memories with hierarchical redundancy,” in Proc. IEEE Int’l Conf. on Computer and Information Science, July 2006, pp. 355–360.
[57] Y.-J. Huang, D.-M. Chang, and J.-F. Li, “A built-in redundancy-analysis scheme for self-repairable RAMs with two-level redundancy,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Oct. 2006, pp. 362–370.
[58] W. Jeong, T. Han, and S. Kang, “An advanced BIRA using parallel sub-analyzers for embedded memories,” in Proc. IEEE International SOC Conference (ISOCC), Nov. 2009, pp. 249–252.
[59] J. Lee, K. Park, and S. Kang, “An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy,” in Proc. IEEE International SOC Conference (ISOCC), Nov. 2009, pp. 353–356.
[60] R.-F. Huang, C.-L. Su, C.-W. Wu, S.-T. Lin, K.-L. Luo, and Y.-J. Chang, “Fail pattern identification for memory built-in self-repair,” in IEEE Asian Test Symp. (ATS), Nov. 2004, pp. 366–371.
[61] W. Xiaopeng, J. Mehler, F. Meyer, and P. Nohpill, “Memory yield and complexity of built-in self-repair,” in Proc. IEEE Int’l Symp. on Reliability and Maintainability, Jan. 2005, pp. 238–244.
[62] R.-F. Huang, J.-F. Li, J.-C. Yeh, and C. W. Wu, “Rainsin: redundancy analysis algorithm simulation,” IEEE Design & Test of Computers, vol. 24, no. 4, pp. 386–396,
July-Aug. 2007.
[63] J. M. Mulder, N. T. Quach, and M. Flynn, “An area model for on-chip memories and its application,” IEEE Jour. of Solid-State Circuits, vol. 26, no. 2, pp. 98–106, Feb. 1991.
[64] Y.-J. Chang, Y.-J. Huang, and J.-F. Li, “A built-in redundancy-analysis scheme for RAMs with 3D redundancy,” in Proc. Int’l Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2011, pp. 1–4.
[65] J. Chung, J. Park, J. A. Abraham, E. Byun, and C.-J. Woo, “Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate,” in Proc. IEEE VLSI Test Symp. (VTS), Apr. 2010, pp. 33–38.
[66] M.-H. Yang, H. Cho, W. Kang, and S. Kang, “EOF:efficient built-in redundancy analysis
methodology with optimal repair rate,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 7, pp. 1130–1135, July 2010.
指導教授 李進福(Jin-fu Li) 審核日期 2012-1-20
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