K/V頻段壓控振盪器暨V頻段三階次諧注入鎖定振盪器之研製

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連子誼(Tzu-Yi Lian) 查詢紙本館藏

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電機工程學系

論文名稱

K/V頻段壓控振盪器暨V頻段三階次諧注入鎖定振盪器之研製
(The Implementations on K/V-Band Voltage Controlled Oscillators and V-Band Third Sub-harmonic Injection Locked Oscillator)

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摘要(中)

本論文包含兩主題，第一部份為壓控振盪器之研製，實現兩個K頻段壓控振盪器及兩個V頻段壓控振盪器。第二部份為注入鎖定式振盪器，實現一個V頻段三階次諧注入鎖定振盪器。以上電路分別使用tsmcTM 0.18 ?m CMOS和90 nm CMOS 及UMCTM 90 nm CMOS製程實現。
第一章介紹研究動機及系統應用，而第二章則介紹兩個K頻段的壓控振盪器架構，使用tsmcTM 0.18 ?m CMOS 製程，第一個電路為閘極至源極回授考畢茲壓控振盪器，此架構設計上為解決傳統考畢茲電路起振不易的問題，設計一轉導提升電路來克服此問題，其中心頻率為21.09 GHz，可調範圍為21.06 到 21.18 GHz，相位雜訊在偏移1 MHz時為 -104.7 dBc/Hz，最大輸出功率為 -9.8 dBm，功率消耗為24.43 mW，計算優化指數為 -177.3 dBc/Hz。第二個電路則延續轉導提升之概念，設計一疊接式轉導提升考畢茲壓控振盪器，其中心頻率為25.0 GHz，可調範圍為24.65 到 25.23 GHz，相位雜訊在偏移1 MHz時為 -97.7 dBc/Hz，最大輸出功率為 -16.17 dBm，功率消耗為9.27 mW，計算優化指數為 -176.3 dBc/Hz。
第三章介紹V頻段壓控振盪器的架構，第一個電路使用UMCTM 90 nm CMOS製程，電路中設計一自我取樣電路，並利用基極效應降低臨界電壓，以達到降低功耗之目標，其中心頻率為 50.7 GHz，可調範圍為50.25 到 51.5 GHz，相位雜訊在偏移10 MHz時為 -123.9 dBc/Hz，最大輸出功率為 -8.34 dBm，功率消耗為25.44 mW，計算優化指數為 -183.9 dBc/Hz。第二個電路使用tsmcTM 90 nm CMOS製程，此電路利用達靈頓對為架構，並使用變壓器回授，使源極端的電壓成為動態，讓電晶體的偏壓可達飽和，其中心頻率為54.23 GHz，可調範圍為53.82 到 55.62 GHz，相位雜訊在偏移10 MHz時為 -113.09 dBc/Hz，最大輸出功率為 -6.14，功率消耗為11.3 mW，計算優化指數為-177.2 dBc/Hz。
第四章介紹V頻段的三階次諧注入鎖定振盪器架構，使用UMCTM 90 nm CMOS製程，此三階次諧注入鎖定振盪器利用兩組回授路徑，其目的為加強三倍頻注入訊號，使三階次諧注入鎖定振盪器能有較寬的鎖頻範圍，量測結果為自振頻率為41.45 GHz，可鎖定範圍為39.32 到 41.91 GHz，功率消耗為19.18 mW，鎖定時相位雜訊在1 MHz時為-114.1 dBc/Hz，最大輸出功率為 -4.17 dBm，優化指標為0.33。
第五章為結論，討論以上晶片優劣處，並設定自己的未來期許和努力方向。

摘要(英)

This thesis studies two subjects. The first one is the design of voltage control oscillator. Two K-band VCOs and two V-band VCOs were designed and implemented. The second one is the design of injection lock oscillator. A V-band third sub-harmonic injection lock oscillator was implemented. Aforementioned circuits were implemented in tsmcTM 0.18 ?m CMOS, 90 nm CMOS and UMCTM 90 nm CMOS technologies.
The thesis is organized as follow, Chapter 1 gives the motivation and induction of system applications. Chapter 2 introduces two K-band VCO topologies which were fabricated in tsmcTM 0.18 ?m CMOS technology. The first circuit is the gate-to-source feedback Coliptts VCO. The proposed gm-boosted technique solves the problem of difficult oscillation of conventional Coliptts VCO. The measured oscillation central frequency is 21.09 GHz with the tunable frequency range from 21.06 to 21.18 GHz. The phase noise is -104.7 dBc/HZ at 1 MHz offset, and the maximum output power is -9.8 dBm. The total power consumption is 24.43 mW. The figure of merit ( FOM ) is -177.3 dBc/Hz. The second circuit continues to improve the gm-boosting ability. The cascode gm-boosted Coliptts VCO is designed. The measured oscillation central frequency is 25.0 GHz with the tunable frequency range from 24.65 to 25.23 GHz. The phase noise is -97.7 dBc/Hz at 1 MHz offset, and the maximum output power is -16.7 dBm. The total power consumption is 9.27 mW. The FOM is -176.3 dBc/Hz.
Chapter 3 presents two V-band VCO topologies. The first circuit was fabricated in UMCTM 90 nm CMOS. This topology provides a self-detected circuit to reduce the threshold voltage. Therefore, this VCO can reduce the power consumption. The measured oscillation central frequency is 50.7 GHz with the tunable frequency range from 50.25 to 51.5 GHz. The phase noise is -123.9 dBc/Hz at 10 MHz offset, and maximum output power is -8.34 dBm. The total power consumption is 25.44 mW. The FOM is -183.9 dBc/Hz. The second circuit was fabricated in tsmcTM 90 nm CMOS. This topology is darlinton pair, and using transformer feedback. Therefore, the source voltage become active. The transistor can work in saturation. The measured oscillation central frequency is 54.23 GHz with tunable frequency range from 53.82 to 55.62 GHz. The phase noise is -113.09 dBc/HZ at 10 MHz offset, and the maximum output power is -6.14 dBm. The total power consumption is 11.3 mW. The FOM is -177.2 dBc/Hz.
Chapter 4 develops a V-band third sub-harmonic injection lock oscillator topology which was fabricated in UMCTM 90 nm CMOS technology. This third sub-harmonic injection lock oscillator used two feedback paths to increase the third-harmonic power. Therefore, it can increase the locking range. The measured free run frequency of oscillator is 41.45 GHz. The locking range is from 39.32 to 41.91 GHz. The power consumption is 19.18mW. The phase noise is -114.1 dBc/Hz at 1 MHz offset which VCO is under injection locked. The maximum output power is -4.17 dBm. The FOM is 0.33.
Finally, the conclusion and future work are given in Chapter 5.

關鍵字(中)

★ 考畢茲
★ 注入鎖定
★ 轉導提升
★ 壓控振盪器

關鍵字(英)

★ voltage control oscillator
★ gm-boosting
★ Colpitts
★ injection lock

論文目次

摘要 i
Abstract iii
誌謝 v
目錄 vi
圖目錄 viii
表目錄 xi
第一章緒論 1
1-1研究動機 1
1-2研究成果 2
1-3章節簡介 2
第二章 K頻段壓控振盪器 3
2-1轉導提升考畢茲壓控振盪器 3
2-1-1簡介 3
2-2閘極至源極回授考畢茲壓控振盪器 5
2-2-1閘極至源極回授考畢茲壓控振盪器設計原理 5
2-2-2量測結果 7
2-2-3比較與討論 11
2-3疊接式轉導提升考畢茲壓控振盪器 12
2-3-1疊接式轉導提升考畢茲壓控振盪器設計原理 12
2-3-2量測結果 15
2-3-3比較與討論 19
第三章 V頻段壓控振盪器 21
3-1自我取樣基極調變壓控振盪器 21
3-1-1簡介 21
3-1-2自我取樣基極調變壓控振盪器設計原理 22
3-1-3量測結果 24
3-1-4比較與討論 28
3-2 變壓器回授達靈頓對壓控振盪器 29
3-2-1簡介 29
3-2-2變壓器回授達靈頓對壓控振盪器設計原理 30
3-2-3量測結果 32
3-2-4比較與討論 36
第四章 V頻段三階次諧注入鎖定振盪器 39
4-1雙回授三階次諧注入鎖定振盪器 39
4-1-1簡介 39
4-1-2雙回授三階次諧注入鎖定振盪器設計原理 40
4.1.3 量測結果 42
4.1.4比較與討論 47
第五章結論 49
5-1 結論 49
5-2 未來期許與研究方向 50
參考文獻 52

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指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2011-8-10

推文