一具有參考頻率刺針抑制功能的5 GHz鎖相迴路

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姓名

張翔皓(Hsiang-Hao Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

一具有參考頻率刺針抑制功能的5 GHz鎖相迴路
(A 5 GHz Phase-Locked Loop with Suppression Reference Spurious Tone Technique)

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摘要(中)

在半導體製程技術的快速發展下，晶片的操作速度越來越快，鎖相迴路現今廣泛的被應用在各種通訊晶片系統中，解決時脈訊號的偏差與延遲，並使得資料能夠正確的被傳送，提供穩定的時脈訊號輸出。
在鎖相迴路的操作中，由於電荷幫浦的電流不匹配、時脈回饋與電荷幫浦開關的電荷注入等不理想的電器特性，造成電荷幫浦中直流與交流電流的週期性影響。這些週期性電流大小變化影響以輸入參考頻率注入迴路濾波器當中，於是電流轉電壓的積分結果在壓控振盪器的控制電壓上造成電壓擾動。此擾動的能量轉換為距離載波能量參考頻率位移旁帶的兩旁，也就是所謂的參考頻率刺針。
本論文提出一具有參考頻率刺針抑制功能的5 GHz鎖相迴路。在窄頻帶調變近似的假設條件下，可以觀察到壓控振盪器的增益KVCO與參考頻率值乃是分別與參考頻率針刺的能量呈現前者正比與後者反比的關係。基於這個原理，本論文呈現了一參考頻率刺針抑制技巧。此電路技巧使用了多頻帶自我校準的電路去降低KVCO，並且加上兩組電流脈波重複(2-PR)與四組脈波位置調變(4-PPM)的抑制技巧增加比較訊號的頻率，分別是使CP的電流脈波頻率成為兩倍與亂數化電流脈波的位置。本論文提出的數位相位選擇器(Digital Phase Selector)實作了上述的參考頻率刺針抑制技巧。因此，在參考頻率為50 MHz的條件下，參考頻率刺針的模擬結果是在5 GHz的載波的50 MHz位移頻率上有78.6 dBc的衰減量，且峰對峰的抖動小於3.9 ps。晶片的核心面積佔0.41 mm2，在供應電壓為1.2V下的總功耗為13.7 mW。

摘要(英)

With the rapid development of semiconductor process technology, the operation frequency of the chip is much more faster than before. PLL is widely used in many communication chip systems to solve the phase error and delay of clock signal. It ensures the date be transferred correctly and provides a steady clock signal.
In terms of the PLL operation, due to the nonidealities such as the charge pump (CP) current mismatch, clock feedthrough, charge injection by the CP switches and so on. Those issues would be periodically covered to dc or ac current, which was injected into the loop filter at the input reference frequency (Fref). Accordingly, the periodic current-to-voltage integration to the control voltage leads to the voltage dithering, and converts such power to both sides of the carrier power at the reference frequency offset, which is so-called reference spur.
A 5 GHz PLL with the suppressive reference spur is presented in this work. Based on the narrowband frequency modulation approximation, it indicates that the gain of the voltage-controlled oscillator (KVCO) and Fref is directly and inversely proportional to the magnitude of the reference spur, respectively. Thus, the suppressive reference spur technique is presented in this work. This technique uses the multi-band calibration scheme to reduce the KVCO gain, as well as collaborates with the two pulse repetition (2-PR) and the four pulse position modulation (4-PPM) to duplicates the frequency of CP current pulses and randomizes such positions, respectively. With regard to the 2-PR and 4-PPM, the proposed digital phase selector (DPS) is realized for such implementation. As a result, by the use of Fref of 50 MHz, the simulated reference spur is attenuated by 78.6 dBc at the 50-MHz frequency offset from the carrier frequency of 5 GHz, and the peak-to-peak jitter is less than 3.9 ps. The chip core area occupies 0.41 mm2, and the total power consumption is around 13.7 mW at supply of 1.2V.

關鍵字(中)

★ 鎖相迴路
★ 參考頻率刺針
★ 電荷幫浦
★ 自我校準電路

關鍵字(英)

★ Phase-Locked Loop
★ Reference Spur
★ Charge Pump
★ Self-Calibration Circuit

論文目次

目錄
摘要 ii
Abstract iii
誌謝 v
目錄 vi
圖目錄 ix
表目錄 xii
第1章緒論 1
1.1 動機 1
1.2 參考頻率刺針簡介 3
1.3 論文架構 5
第2章鎖相迴路之基本觀念 7
2.1 鎖相迴路的組成元件與操作原理 7
2.1.1 相位頻率偵測器 (PFD) 8
2.1.2 充放電幫浦 (CP) 9
2.1.3 迴路濾波器 (LPF) 10
2.1.4 電壓控制振盪器 (VCO) 10
2.1.5 除頻器 (FD) 11
2.2 鎖相迴路的迴路分析 12
第3章具有參考頻率刺針抑制功能的鎖相迴路 21
3.1 抑制參考頻率刺針能量之電路技巧相關文獻 21
3.1.1 多頻帶壓控振盪器 (Multi-band Voltage Control Oscillator) 23
3.1.2 延遲取樣電壓週期擾動 (Delay-sampling the Control Voltage) 24
3.1.3 降低電荷幫浦的不匹配現象 (Minimizing the CP Mismatch) 25
3.1.4 實作多組電荷幫浦與相位頻率偵測器 (Distributed PFDs and CPs) 26
3.1.5 脈波位置調變 (Pulse Position Modulation) 27
3.2 脈波位置調變與脈波重複數學模型 (Mathematical Model of PPM and PR) 29
3.2.1 脈波位置與振幅調變 (Pulse Position and Amplitude Modulation) 29
3.2.2 參考頻率刺針能量抑制效果與延遲誤差百分比 (Reference Spur Reduction with Percentage of Delay Error) 32
3.2.3 脈波位置調變與脈波重複 (Pulse Position Modulation and Pulse Repetition) 34
第4章具有參考頻率刺針抑制功能的5 GHz鎖相迴路的設計與實作 37
4.1 具有參考頻率刺針抑制功能鎖相迴路的操作原理 37
4.2 具有參考頻率刺針抑制功能鎖相迴路的組成元件 40
4.2.1 可控式相位頻率偵測器 (C-PFD) 40
4.2.2 充放電幫浦 (CP) 42
4.2.3 互補式交叉耦合電感電容電壓控制振盪器 (LC-VCO) 44
4.2.4 迴路濾波器 (LPF) 47
4.2.5 除頻器 (FD) 47
4.2.6 鎖定偵測電路 (Locked Detector) 50
4.3 壓控振盪器校正電路(VCO Calibration) 51
4.4 數位相位選擇器(Digital Phase Selector) 56
4.4.1 同步延遲線(Synchronous Delay Line) 57
4.4.2 消除突波多工器(Deglitch Multiplexer) 61
4.5 5-GHz鎖相迴路的模擬結果 63
4.5.1 佈局前模擬(Pre-layout simulation) 63
4.5.2 佈局後模擬(Post-layout simulation) 65
第5章鎖相迴路的佈局與量測考量 69
5.1 鎖相迴路之電路佈局 69
5.2 鎖相迴路的量測考量 71
5.3 文獻比較 74
第6章結論 77
6.1 結論 77
參考文獻 79

參考文獻

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2012-11-30

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