參考文獻 |
[1] Behzad Razavi, “Challenges in the Design of Frequency Synthesizers for Wireless Application,” in Proceedings of the IEEE 1997 Custom Integrated Circuits Conference, May 1997, pp. 395-402
[2] Chembiyan Thambidurai and Nagendra Krishnapura, “On Pulse Position Modulation and Its Application toPLLs for Spur Reduction,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 7, Jul. 2011.
[3] B. Razavi, “Design of Analog CMOS Integrated Circuit,” New York: McGraw-Hill, 2001.
[4] Nakamura, T. et al., “A Wide-tuning-range VCO with Small VCO-gain Fluctuation for Multi-band W-CDMA RFIC,” in Proc. ESSCIRC (ESSCIRC), 2006 Proceedings of the 32nd European, Sep. 2006, pp. 448-451
[5] Che-Fu Liang, Hsin-Hua Chen, and Shen-Iuan Liu, “Spur-Suppression Techniques for Frequency Synthesizers,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 8, Aug. 2007.
[6] Che-Fu Liang, Shin-Hua Chen, and Shen-Iuan Liu, “A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems,” IEEE J. Solid-State Circuits, vol. 43, no. 2, Feb. 2008.
[7] Tai-Cheng Lee and Wei-Liang Lee,“A Spur Suppression Technique for Phase-Locked Frequency Synthesizers,” in Proceedings of IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 2006, pp. 2432-2441
[8] Chembiyan Thambidurai and Nagendra Krishnapura, “Spur Reduction in Wideband PLLs by Random Positioning of Charge Pump Current Pulses,”in IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2010, pp. 3397-3400
[9] Jaehyouk Choi, Woonyun Kim, and Kyutae Lim, “A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL,” IEEE Trans. Very Large Scale Integration(VLSI) Systems, vol. 20,no. 5, pp.969-973, May 2012.
[10] Cameron T. Charles and David J. Allstot, “A Calibrated Phase/Frequency Detector for Reference Spur Reduction in Charge-Pump PLLs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 9, Sep. 2006.
[11] K. Ha and L. Kim, “Charge-pump reducing current mismatch in DLLs and PLLs,” in Proceedings of IEEE Int. Symp. on Circuits and Systems (ISCAS), Jun. 2006, pp. 2221–2224
[12] De-Wen Liao and Chung-Chih Hung, “A Spur-Reduction Frequency Synthesizer For WIMAX Applications ,” in Proceedings of IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2010, pp. 2594-2597
[13] Elsayed, M.,” A Spur-Frequency-Boosting PLL with a −74dBc reference-spur rejection in 90nm digital CMOS,” in Proceedings of IEEE Radio Frequency Integrated Circuits Symp., Jun. 2011, pp.1-4
[14] Rafaella Fiorelli et al., " LC-VCO Design Optimization Methodology Based on the Ratio for Nanometer CMOS Technologies," IEEE Trans. Microwave Theory and Technique, pp. 1822-1831, July 2011
[15] Richard Gu et al.,“A 6.25GHz 1V LC-PLL in 0.13 m CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 2006, pp. 2442-2451
[16] T.H. Lin and W.J. Kaiser, “A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop,” IEEE J. Solid-State Circuit, pp. 424-431, Mar. 2001.
[17] S.M. Paletmo and J.P. de Gyve, “A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO,” in Proceedings of IEEE Midwest Symp. on Circuits and Syst., 2000, pp. 818-821
[18] C. Y. Kuo, J. Y. Chang, and S. I. Liu, “A spur-reduction technique for a 5-GHz frequency synthesizer,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 3, pp. 526–533, Mar. 2006.
[19] Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Han Jimmy Liu, Kai-Wei Hong, and Chin-Cheng Kuo,“A low jitter self-calibration PLL for 10-Gbps SoC transmission lines application,”IEICE Trans. Electron ,pp.786-789, Jan. 2009
[20] Xiang Gao et al., “Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector,” IEEE J. Solid-State Circuits, vol.45, no.9, pp. 1809–1821, Sep. 2010
[21] Elsayed, M.,” A Spur-Frequency-Boosting PLL with a −74dBc reference-spur rejection in 90nm digital CMOS,” in IEEE Radio Frequency Integrated Circuits Symp., Jun. 2011, pp.1-4
[22] Fang-Ren Liao et al.,“A Programmable Edge-Combining DLL With a Current-Splitting Charge Pump for Spur Suppression,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 12, Dec. 2010.
[23] Kevin J. Wang, Ashok Swaminathan, and Ian Galton, “Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL,” IEEE J. Solid-State Circuits, vol. 43, no. 12, Sep. 2008.
[24] Pin-En Su and Sudhakar Pamarti, “A 2-MHz Bandwidth Δ-Σ Fractional-N Synthesizer Based On a Fractional Frequency Divider with Digital Spur Suppression,”in IEEE Radio Frequency Integrated Circuits Symp.,May 2010,pp.413-416
[25] Xiang Gao et al.,“ Spur-Reduction Techniques for PLLs Using Sub-Sampling Phase Detection,”in IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 2010, pp.474-475
[26] S. Pellerano, S. Levantino, C. Samori, and A. L. Lacaita, “A 13.5-mW 5-GHz frequency synthesizer with dynamic-Logic frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 378–383, Feb. 2004.
[27] Pin-En Su, and Sudhakar Pamarti, “Mismatch Shaping Techniques to Linearize Charge Pump Errors in Fractional-N PLLs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 6, pp. 1221–1230, June. 2010.
[28] Sander L. J. Gierkink , “Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2967–2976, Dec. 2008.
[29] Prabir C. Maulik, and Douglas A. Mercer, “A DLL-Based Programmable Clock Multiplier in 0.18- m CMOS With -70 dBc Reference Spur,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1642–1648, Aug. 2007.
|