旋積盲訊號源分離之超大型積體電路架構設計

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：6

、訪客IP：3.144.28.50

姓名

黃紹傑(Shao-Chieh Huang) 查詢紙本館藏

畢業系所

資訊工程學系

論文名稱

旋積盲訊號源分離之超大型積體電路架構設計
(VLSI architecture design for Convolutive Blind Source Separation)

相關論文

★ Single and Multi-Label Environmental Sound Recognition with Gaussian Process	★ 波束形成與音訊前處理之嵌入式系統實現
★ 語音合成及語者轉換之應用與設計	★ 基於語意之輿情分析系統
★ 高品質口述系統之設計與應用	★ 深度學習及加速強健特徵之CT影像跟骨骨折辨識及偵測
★ 基於風格向量空間之個性化協同過濾服裝推薦系統	★ RetinaNet應用於人臉偵測
★ 金融商品走勢預測	★ 整合深度學習方法預測年齡以及衰老基因之研究
★ 漢語之端到端語音合成研究	★ 基於 ARM 架構上的 ORB-SLAM2 的應用與改進
★ 基於深度學習之指數股票型基金趨勢預測	★ 探討財經新聞與金融趨勢的相關性
★ 基於卷積神經網路的情緒語音分析	★ 運用深度學習方法預測阿茲海默症惡化與腦中風手術存活

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 ( 永不開放)

摘要(中)

獨立訊號經過旋積混合後的盲訊號源分離問題，發生在很多實際的應用上，我們希望提供一個高效能與可延展的旋積盲訊號源分離電路架構。在演算法上，我們使用Torkkola所提出的架構來實現旋積盲訊號源分離，Torkkola的學習規則近似於最小均方誤差演算法，因為要增加硬體的時脈速度與吞吐率必需減少關鍵路徑長度，所以我們也利用近似於最小均方誤差適應性濾波器的延遲最小均方誤差適應性濾波器來做修改應用到旋積盲訊號源分離中。本論文在延遲最小均方誤差適應性濾波器中，提出了兩種架構，第一種架構大幅改進了適應延遲，在大部分的情況維持3個延遲，並且關鍵路徑也維持在一個乘法與一個加法。第二種架構利用分享乘法器的方法改進了適應延遲與關鍵路徑，大部分的情況只需要6個延遲，而且關鍵路徑只要一個預處理單元，處理時間較一個乘法時間為低，此外我們提出的兩個架構也將延遲數與濾波器長度的影響降低。我們所提出之旋積盲訊號源分離架構主要架構於上述兩者之上，在演算法上，分別針對向前式與回授式這兩種型式。我們讓延遲最小均方誤差適應性濾波器模組化以及維持了它的關鍵路徑長度，是一個兼具可延展與高效能的旋積盲訊號源分離電路架構。

摘要(英)

Blind source separation (BSS) of independent sources from their convolutive mixtures is a problem in many real world applications. Therefore, we hope we can design an effective and scalable VLSI architecture for BSS. Considering the algorithm, the BSS architecture proposed by Torkkola is utilized and its learning rule is similar to least mean squares (LMS). Reducing the critical path will increase clock rate and throughput of hardware, so we apply delayed LMS (DLMS) to BSS. We proposed two VLSI architectures for DLMS. The proposed-I architecture improves the adaptation delays. In most of the cases, we maintain 3 adaptation delays and maintain the critical path as one adder and one multiplication. The proposed-II architecture based on sharing multiplication improves adaptation delays and critical path. In most of the cases, we only need 6 adaptation delays. Because critical path only passes precomputer bank, the critical path is less than 1Tm. Besides, we reduce the effect of delays and filter length in the two propose methods. The proposed VLSI design for BSS is based on the above two presented DLMS architecture. Moreover, both feedforward and feedback BSS algorithms are adopted respectively. Because the designed DLMS is modular and its critical path is maintained, the proposed VLSI architecture for convolutive blind source separation is scalable and effective.

關鍵字(中)

★ 延遲最小均方誤差
★ 適應性濾波器
★ 旋積盲訊號源分離

關鍵字(英)

★ Convolutive Blind Source Separation
★ DLMS
★ Adaptive filter

論文目次

Abstract in Chinese i
Abstract in English ii
Acknowledge iii
Content iv
List of Figures vi
List of Tables ix
Chapter 1 Introduction 1
1.1 Motivation……………………………………… 1
1.2 Purposes………………………………………… 1
1.3 Organization…………………………………… 2
Chapter 2 Blind Source Separation(BSS) 3
2.1 Introduction to BSS………………………… 3
2.2 Mixing Model…………………………………… 4
2.2.1 Special Case…………………………………… 5
2.2.2 Convolutive model in the frequency domain… 7
2.3 Separation Model………………………………… 7
2.3.1 Feedforward Structure…………………………… 8
2.3.2 Feedback Structure……………………………… 9
2.3.3 Two Input Two Output System………………… 10
2.4 Separation Principle……………………………… 11
2.4.1 Independent Component Analysis (ICA) and BSS 12
2.4.2 Information- Maximization…………………… 12
2.5 Related VLSI BSS architectures………………… 16
Chapter 3 Delayed Least Mean Square Filter 17
3.1 Introduction to Adaptive Filter………………… 17
3.2 Least Mean Square (LMS) Filter……………… 18
3.3 Delayed Least Mean Square (DLMS) Filter… 22
3.4 Related VLSI DLMS Architectures…………… 24
Chapter 4 VLSI Architecture for Convolutive BSS 31
4.1 Improved VLSI DLMS Architectures………… 32
4.1.1 The Proposed Architecture-I…………………… 32
4.1.2 The Proposed Architecture-II…………………… 45
4.1.3 Comparison Results…………………………… 53
4.2 The Whole VLSI BSS Architecture…………… 55
Chapter 5 Conclusion 62
Reference 63

參考文獻

[1] K. Matsubara, K. Nishikawa, and H. Kiya, “Pipelined LMS adaptive filter using a new look-ahead transformation,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no.1, pp.51-55, Jan. 1999.
[2] S.C. Douglas, Zhu Quanhong, K.F. Smith, “A pipelined LMS adaptive FIR filter architecture without adaptation delay,” IEEE Transactions on Signal Processing, vol. 46, no.3, pp.775-779, Mar. 1998.
[3] G. Long, F. Ling, J.G. Proakis, “The LMS algorithm with delayed coefficient adaptation,” IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 37, no.9, pp.1397-1405, Sep. 1989.
[4] G. Long, F. Ling, J.G. Proakis, “Corrections to `The LMS algorithm with delayed coefficient adaptation,” IEEE Transactions on Signal Processing, vol. 40, no.1, pp.230-232, Jan. 1992.
[5] M.D. Meyer, D.P. Agrawal, “A high sampling rate delayed LMS filter architecture,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 40, no.11, pp.727-729, Nov. 1993.
[6] H. Herzberg, R. Haimi-Cohen, “A systolic array realization of an LMS adaptive filter and the effects of delayed adaptation,” IEEE Transactions on Signal Processing, vol. 40, no.11, pp.2799-2803, Nov. 1992.
[7] L.D. Van, W.S. Feng, “An efficient systolic architecture for the DLMS adaptive filter and its applications,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.48, no.4, pp.359-366, Apr. 2001.
[8] B. Widrow, J.M. McCool, M.G. Larimore, C.R. Johnson, Jr., “Stationary and nonstationary learning characteristics of the LMS adaptive filter,” Proceedings of the IEEE, vol.64, no.8, pp. 1151- 1162, Aug. 1976.
[9] H.T. Kung, W.L. Lin, “An algebra for VLSI algorithm design,” in:Proceedings of Conference Elliptic Solvers(Monterey, CA), January 1983; also Research Report CMU-CS-84-1000, Department of Computer Science, Carnegie-Melon University, Pittsburg, PA, April 1983.
[10] K.K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, New York: Wiley, 1999, ch. 10.
[11] K. Torkkola, “Blind separation of convolved sources based on information maximization,” Neural Networks for Signal Processing [1996] VI. Proceedings of the 1996 IEEE Signal Processing Society Workshop, vol., no., pp.423-432, 4-6 Sep. 1996.
[12] A.J. Bell, T.J. Sejnowski, “Blind separation and blind deconvolution: an information-theoretic approach,” 1995 International Conference on Acoustics, Speech, and Signal Processing, 1995. ICASSP-95., vol.5, no., pp.3415-3418 vol.5, 9-12 May. 1995.
[13] M.S. Pedersen, J. Larsen, U. Kjems, and Lucas C. Parra, “A Survey of convolutive blind source separation methods,” Springer Handbook on Speech Processing and Speech Communication, 2007.
[14] A. Hyvärinen, E. Oja., Independent Component Analysis: Algorithms and Applications., Neural Networks, 13(4-5):411-430, 2000.
[15] K.S. Cho, S.Y. Lee, “Analog CMOS implementation of nonholonomic ICA algorithm with automatic offset compensation,” 2003. Proceedings of the 2003 International Conference on Neural Networks and Signal Processing, vol.1, no., pp. 279- 282 vol.1, 14-17 Dec. 2003.
[16] M. Ounas, R. Touhami, M.C.E. Yagoub, “Low Cost Architecture of Digital Circuit for FPGA Implementation Based ICA Training Algorithm of Blind Signal Separation,” 2007. ISSSE '07. International Symposium on Signals, Systems and Electronics, vol., no., pp.135-138, July 30 2007-Aug. 2 2007.
[17] F. Sattar, C. Charayaphan, “Low-cost design and implementation of an ICA-based blind source separation algorithm,” 2002. 15th Annual IEEE International ASIC/SOC Conference, vol., no., pp. 15- 19, 25-28 Sept. 2002.
[18] M.M. Mano, C. Kime, Logic and Computer Design Fundamentals (4-th Edition), Pearson, 2008.
[19] J. Park, K. Muhammad, K. Roy, “High-performance FIR filter design based on sharing multiplication,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.11, no.2, pp.244-253, April. 2003.
[20] A. Hyvarinen, J. Karhunen, and E. Oja, Independent Component Analysis. Wiley, 2001.
[21] S. Roberts and R. Everson, Independent Components Analysis: Principles and Practice. Cambridge University Press, 2001.
[22] J. Xi, J.P. Reilly, “Blind separation and restoration of signals mixed in convolutive environment,” 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., vol.2, no., pp.1327-1330 vol.2, 21-24 Apr. 1997.
[23] J.P. Reilly, L.C. Mendoza, “Blind signal separation for convolutive mixing environments using spatial-temporal processing,” 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing, 1999. ICASSP '99. Proceedings., vol.3, no., pp.1437-1440 vol.3, 15-19 Mar. 1999.
[24] K. Torkkola, “Blind separation of delayed and convolved sources,” In S. Haykin, editor, Unsupervised Adaptive Filtering, Vol. I, pages 321-375. Wiley, 2000.
[25] M. Ounas, S. Chitroub, R. Touhami, M. Yagoub, S. Gaoua, “Digital circuit design for FPGA based implementation of ICA for real time Blind Signal Separation,” International Conference on Microelectronics, 2008. ICM 2008., vol., no., pp.60-63, 14-17 Dec. 2008.
[26] A. Hyvarinen, J. Karhunen, and E. Oja, Independent Component Analysis, John Wiley,2001.
[27] Z. Li, Q. Lin, “FPGA Implementation of Infomax BSS Algorithm with Fixed-Point Number Representation,” International Conference on Neural Networks and Brain, 2005. ICNN&B '05., vol.2, no., pp.889-892, 13-15 Oct. 2005.
[28] A.B. Lim, J.C. Rajapakse, A.R. Omondi, “Comparative study of implementing ICNNs on FPGAs,” International Joint Conference on Neural Networks, 2001. Proceedings. IJCNN '01., vol.1, no., pp.177-182 vol.1, 2001.
[30] K.S. Cho, S.Y. Lee, “Analog CMOS implementation of nonholonomic ICA algorithm with automatic offset compensation,” Proceedings of the 2003 International Conference on Neural Networks and Signal Processing, 2003., vol.1, no., pp. 279- 282 Vol.1, 14-17 Dec. 2003.
[31] C. Charoensak, F. Sattar, “A single-chip FPGA design for real-time ICA-based blind source separation algorithm,” IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005., vol., no., pp. 5822- 5825 Vol. 6, 23-26 May. 2005.
[32] C. Charoensak, F. Sattar, “System-level design of low-cost FPGA hardware for real-time ICA-based blind source separation,” Proceedings. IEEE International SOC Conference, 2004., vol., no., pp. 139- 140, 12-15 Sept. 2004.
[33] H. T. Kung, “Why systolic architectures?,” IEEE Computer, vol. 25, pp. 37-46, Jan. 1982.

指導教授

王家慶(Jia-Ching Wang)

審核日期

2011-8-21

推文