具可變倍率可適性相位頻率偵測器之快速鎖定鎖相迴路

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姓名

陳信圭(Hsin-Kuei Chen) 查詢紙本館藏

畢業系所

電機工程學系在職專班

論文名稱

具可變倍率可適性相位頻率偵測器之快速鎖定鎖相迴路
(A Fast-locking Phase-locked Loop with a Variable Magnification Adaptive Phase Frequency Detector)

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摘要(中)

本論文設計一個具快速鎖定的鎖相迴路，電路中之振盪器由四級雙端延遲元件所組成，可提供八個相位振盪頻率為2.5 GHz的輸出訊號，整體電路架構採用了多頻帶的電壓控制振盪器以在製程、電壓及溫度(Process Voltage and Temperature，PVT)漂移的條件下都能追鎖到目標頻率並且降低增益(KVCO)。為了加速追鎖過程則提出了具可變倍率之可適性相位頻率偵測器，使控制電壓能較為迅捷地改變，藉此快速消弭相位差，達到快速鎖定的效果。
本論文實現之具可變倍率可適性相位頻率偵測器之快速鎖定鎖相迴路使用CIC 0.18 μm CMOS 1P6M教育製程來實現，電路操作電壓為1.8 V。鎖相迴路的輸入參考時脈為50 MHz，輸出頻率鎖定在2.5 GHz，鎖定時輸出時脈抖動量為6.62 ps (峰對峰值)。鎖定時間為2.59 μs，功率消耗為14.2 mW，晶片面積為660 660 μm2，核心電路部分面積則為380 400 μm2。

摘要(英)

In this thesis, a fast locking PLL is designed. Its oscillator is composed of 4-stage differential delay cells and can output 8 phase, 2.5 GHz clock signals. The oscillator adopts multi-band architecture to locked the target frequency in process、voltage and temperature drift conditions, and lower the gain of the voltage controlled oscillator (KVCO). The variable magnification adaptive phase frequency detector speed up the tracking so that the control voltage could vary agilely and the phase difference could be eliminated rapidly.
This study was implemented by CIC 0.18 μm CMOS 1P6M education process with 1.8 V supply voltage. A 50 MHz clock is used to be input reference clock of PLL, and the output frequency is 2.5 GHz. The period jitter of output frequency is 6.62 ps (peak-to-peak). The locking time of the proposed PLL is 2.59 μs at 2.5 GHz and the power consumption of the PLL is 14.2 mW. The chip area is 660 660 μm2 and the core area is 380 400 μm2.

關鍵字(中)

★ 快速鎖定
★ 鎖相迴路

關鍵字(英)

論文目次

摘要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 vii
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 2
第2章快速鎖定鎖相迴路背景簡介 3
2.1 鎖相迴路簡介 3
2.1.1 鎖相迴路的組成元件 3
2.1.2 鎖定的條件 4
2.1.3 規格考量 4
2.2 快速鎖定機制的不同做法 5
2.2.1 使用非線性/分段線性相位頻率偵測器之快速鎖定鎖相迴路[1][2][12] 5
2.2.2 使用邊緣遺失補償器之寬鎖定範圍快速鎖定鎖相迴路[3][12] 6
2.2.3 使用動態相位補償技術之快速鎖定鎖相迴路[4][12] 7
2.2.4 各種做法的比較 9
第3章快速鎖定鎖相迴路系統分析 11
3.1 設計考量 11
3.2 加速鎖定機制設計架構說明 11
3.3 設計規格 13
3.4 迴路穩定度分析 14
3.4.1 基本鎖相迴路系統分析 14
3.4.2 快鎖機制對穩定度影響的分析 17
第4章快速鎖定鎖相迴路電路設計 19
4.1 電路架構 19
4.2 快速鎖定鎖相迴路子電路介紹 21
4.2.1 可適性相位頻率偵測器(Adaptive Phase Frequency Detector，APFD) 21
4.2.2 多頻帶自我校準電路(Multi-Band Self Calibration Circuit，MSCC) 26
4.2.3 單端轉雙端電路 (Single to Differential，S2D) 29
4.2.4 電荷幫浦 (Charge Pump，CP) 30
4.2.5 迴路濾波器 (Loop Filter，LF) 31
4.2.6 電壓控制振盪器 (Voltage Control Oscillator，VCO) 32
4.2.7 雙端轉單端電路 (Differential to Single，D2S) 35
4.2.8 除頻器 (Divider) 36
第5章晶片模擬結果 38
5.1 快速鎖定鎖相迴路模擬結果 38
5.1.1 加速機制模擬結果 38
5.1.2 全電路模擬結果 39
5.2 與相關文獻鎖定時間FOM之比較 42
5.3 晶片佈局 44
5.4 輸入輸出模型 48
5.5 電路規格 50
第6章結論與未來研究方向 51
6.1 結論 51
6.2 未來研究方向 51
參考文獻 i

參考文獻

[1] Jinbao Lan, Fengchang Lai, Zhiqiang Gao, Hua Ma and Jian wei Zhang, “A nonlinear phase frequency detector for fast-lock phase-locked loops”, IEEE 8th International Conference ASIC, pp. 1117-1120, 2009.
[2] N. E. Seraji and M. Yavari, “Piecewise-linear phase frequency detector for fast-lock phase-locked loops,” in Proc. IEEE Int. Midwest Symposuim on Circuits and System (MWSCAS), Aug. 2011.
[3] Chi-Sheng Lin, Ting-Hsu Chien, Chin-Long Wey, Chun-Ming Huang, and Ying-Zong Juang, “An edge missing compensator for fast settling wide locking range phase- locked loops,” IEEE J. Solid-State Circuits, vol.44, no.11, pp.3102–3109, Nov. 2009.
[4] Wei-Hao Chiu, Yu-Hsiang Huang, Tsung-Hsien Lin, “A dynamic phase error compensation technique for fast-locking phase-locked loops,” IEEE J. Solid-State Circuits, vol.45, no.6, pp.1137–1148, Jun. 2010.
[5] 劉深淵, 楊清淵, 鎖相迴路, 滄海書局, 2006
[6] Chao-Ching Hung and Shen-Iuan Liu, “A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modiﬁed Bang-Bang Algorithm,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 58, no. 6, pp. 321–325, Jun. 2011.
[7] Jaewook Shin and Hyunchol Shin, “A 1.9–3.8 GHz Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 665–675, Mar. 2012.
[8] Kyoungho Woo, Yong Liu, Eunsoo Nam, and Donhee Ham, “Fast-Lock Hybrid PLL Combining Fractional-N and Integer-N Modes of Different Bandwidths,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 379–389, Feb. 2008.
[9] Bo Zhao, Yong Lian, and Huazhong Yang, “A Low-Power Fast-Settling Bond-Wire Frequency Synthesizer With a Dynamic-Bandwidth Scheme,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 60, no. 5, pp. 1188–1199, May 2013.
[10] Mohammad Hekmat, Farshid Aryanfar, Jason Wei, Vijay Gadde, and Reza Navid, “A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators,” IEEE J. Solid-State Circuits, vol.50, no.2, pp.490–502, Feb. 2015.
[11] Jung-Mao Lin, and Ching-Yuan Yang, “A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment, “A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 62, no.10, pp. 2411–2422, Oct 2015.
[12] 李柏逸, “具數位頻帶選擇器和可適性相位頻率偵測器之快速鎖定鎖相迴路,” 國立中央大學, 碩士論文, 國立中央大學, 2013
[13] Hui Dong Lee; Nam-Sik Ryu; Jae-Ho Jung; Kwang Chun Lee, “A 2.9-GHz LC-VCO based PLL with a Fast Automatic Frequency Control,” in Proc. IEEE Int. Symp. Wireless Commun. Syst.(ISWCS), Aug. 2012, pp. 860–864.
[14] Yun-Ta Tsai, Shen-Iuan Liu, “A fast-locking phase-locked loop using CP control and Gated VCO”, in Proc. IEEE VLSI-DAT Symp., Apr. 2012, pp. 1-4
[15] Song-Yu Yang, Wei-Zen Chen, and Tai-You Lu, “A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconﬁgured Digital Loop Filter in 90 nm CMOS Technology,” IEEE J. Solid-State Circuits, vol.45, no.3, pp.578–586, Mar. 2010.
[16] Yuanfeng Sun, Xueyi Yu, Woogeun Rhee, Dawn Wang, and Zhihua Wang, “A Fast Settling Dual-Path Fractional- PLL With Hybrid-Mode Dynamic Bandwidth Control,” IEEE Microw. Wireless Compon. Lett., vol. 20, no.8, pp. 462–464, Aug. 2010.
[17] Woo-Yeol Shin, Manho Kim, Gi-Moon Hong, and Suhwan Kim, “A Fast-Acquisition PLL using Split Half-Duty Sampled Feedforward Loop Filter,” IEEE Trans. Consμmer Electron., vol. 56, no.3, pp. 1856-1859, Aug. 2010.
[18] Liang Wang, Qirong Jiang, Lucheng Hong, Chunpeng Zhang, and Yingdong Wei, “A Novel Phase-Locked Loop Based on Frequency Detector and Initial Phase Angle Detector,” IEEE Trans. Power Electron., vol. 28, no. 10, pp. 4538–4549, Oct. 2013.
[19] Giuseppe Fedele, Ciro Picardi, and Domenico, “A Power Electrical Signal Tracking Strategy Based on the Modulating Functions Method,” IEEE Trans. Ind. Electron., vol. 56, no. 10, pp. 4079–4087, Oct. 2009.
[20] Shinji Shinnaka, “A Robust Single-Phase PLL System With Stable and Fast Tracking,” IEEE Trans. Ind. Appl., vol. 44, no. 2, pp. 624–633, Mar./Apr. 2008.
[21] Ling Luo, Nathan M. Neihart, Sμmit Roy, and David J. Allstot, “A Two-Stage Sensing Technique for Dynamic Spectrμm Access,” IEEE. Trans. Wireless Commun., vol. 8, no.6, pp. 3028-3037, Jun. 2009.
[22] Saeed Golestan, Mohammad Monfared, and Francisco D. Freijedo, “Design-Oriented Study of Advanced Synchronous Reference Frame Phase-Locked Loops,” IEEE Trans. Power Electron., vol. 28, no. 2, pp. 765–778, Feb. 2013.
[23] Saeed Golestan, Mohammad Monfared, Francisco D. Freijedo, and Josep M. Guerrero, “Dynamics Assessment of Advanced Single-Phase PLL Structures,” IEEE Trans. Ind. Electron., vol. 60, no. 6, pp. 2167–2177, Jun. 2013.
[24] Chin-Cheng Kuo, Meng-Jung Lee, Chien-Nan (Jimmy) Liu, and Ching-Ji Huang, “Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 56, no. 6, pp. 1160–1172, Jun. 2009.
[25] M. Nakamura, A. Yamagishi, M. Harada, M. Nakamura and K. Kishine, “Fast-acquisition PLL using fully digital natural-frequency-switching technique,” IEE Electronics Letters, vol. 44, no. 4, pp. 267-268 , Feb. 2008.

指導教授

鄭國興

審核日期

2016-7-26

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