應用於V-頻段射頻收發機前端電路之低功耗源極注入式混頻器之研製

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姓名

周泓廷(Hung-Ting Chou) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於V-頻段射頻收發機前端電路之低功耗源極注入式混頻器之研製
(The Implementation on Ultra-Low Power Source-Driven Mixers for V-Band RF Transceiver Front-end)

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摘要(中)

本篇論文主要設計導向為應用於V-頻段射頻收發機前端電路之源極注入式混頻器之設計與研製，論文主軸包含一顆主動式升頻混頻器以及一顆主動式降頻混頻器，並以90奈米互補式金屬氧化物半導體製程研製而成。整體電路設計概念主要以低電壓及低功率消耗操作之應用，並以高轉換增益、良好線性度與較佳隔離度等方向作為設計目標。
本篇論文第三章提出一顆低電壓、低功率消耗操作之新式升頻混頻器電路並以台積電(TSMC)標準90奈米互補式金屬氧化物半導體製程研製而成，主要電路架構由偽差動對源極注入式混頻器電路以及電流再生技術所建構而成。在電路設計概念上，將升頻混頻器電路操作於接近弱反轉區，使得整體電路在供應電壓為0.4 V時，其消耗功率只有149 W，同時，此混頻器電路亦可在毫米波頻段上保有較佳之電路性能。此電路架構經由實際量測後可獲得-0.62 dB之轉換增益(conversion gain)與-4 dBm之輸出三階截斷點(output third-intercept point: OIP3)且其3-dB操作頻寬範圍為17.5至22.3 GHz。在供應電壓為0.3 V時，整體電路之最佳性能指數(Figure of Merit : FOMUp-M)經由計算可達到33.2。此外，整體晶片尺寸大小為0.72 mm2。
第四章則是介紹一顆微瓦特源極注入式降頻混頻器結合一寬頻非對稱式堆疊耦合架構之馬遜巴倫並以聯電(UMC)低功率90奈米互補式金屬氧化物半導體製程研製而成。在電路設計概念上，此降頻混頻器採用基體偏壓控制技術進而降低整體電路所需之臨界電壓(threshold voltage ; VTH)與供應電壓，藉以達到此毫米波主動式降頻混頻器能操作在接近於弱反轉區之設計目標。再者，為有效縮小整體電路晶片尺寸大小，本篇論文成功研製出一顆寬頻非對稱式堆疊耦合架構之馬遜巴倫，整體3-dB頻寬可達到103 GHz (頻寬範圍從34 GHz至137 GHz)，且在58 GHz時，此巴倫具有3.66 dB之最低插入損耗(3 dB為理想插入損耗值)。而整體馬遜巴倫之晶片尺寸大小為0.016 mm2。經由實際電路量測後，此降頻混頻器在55 GHz時可獲得4.2 dB之最高轉換增益與14.3 dBm之輸入三階截斷點(input third-intercept point: IIP3)。此時，其本地振盪輸入功率(LO power)為2 dBm。在供應電壓為0.5 V時，所流過之直流電流為278 A且整體電路之消耗功率只有139 W。整體降頻混頻器電路之晶片尺寸大小為0.72 mm2，其中亦包含兩顆非對稱式堆疊耦合架構之馬遜巴倫。此外，所提出之源極注入式降頻混頻器可有效操作在低供應電壓及低消耗功率之應用下，因此，其最佳性能指數(FOMDown-M1)可達到39.1。

摘要(英)

This thesis is primarily targeted to design and implement the key component, mixer, for V-band radio frequency (RF) transceiver front-end using source-driven technology. There are two source-driven mixers are investigated based on 90-nm CMOS process that include both up-conversion and down-conversion topologies. The main design goals aim towards high conversion gain (CG), linearity, and port-to-port isolations under ultra-low voltage low power operations.
In the thesis, Chapter 3 proposes a novel up-conversion mixer with pseudo-differential and current-reused topology in TSMC standard 90 nm CMOS technology. The proposed source-pumped up-conversion mixer can operate at near weak inversion under a power consumption of 149 W from a 0.4-V supply voltage while maintains acceptable circuit performance at millimeter-wave (MMW) frequencies. The up-conversion mixer achieves a -0.62 dB conversion gain and a -4 dBm OIP3 in measurements. The measured 3-dB frequency bandwidth ranges from 17.3 to 22.5 GHz. The best figure-of-merit (FOMUp-M) acquires as high as 33.2 under a 0.3-V supply. The chip size including all pads and dummy blocks is 0.72 mm2.
Chapter 4 proposes a microwatt (W) source-driven down-conversion mixer with broadband asymmetrical broadside-coupled baluns in UMC 90-nm CMOS low-power (LP) process. The forward body biased (FBB) technique reduces the threshold voltage (VTH) and supply voltage for operation in the near weak inversion region in MMW active mixer designs. To effectively reduce the size of the chip, an asymmetrical broadside-coupled balun is developed with a bandwidth (BW) of 103 GHz (from 34 to 137 GHz) with a low insertion loss of 3.66 dB (3 dB for an ideal balun) at 58 GHz. The chip area of the balun is 0.016 mm2. The proposed FBB mixer has a 4.2-dB peak CG and a 14.3-dBm input IP3 at 55 GHz under a 2-dBm LO power input. The DC power of the FBB mixer core is only 139 W, while it draws a 278-A DC current from a 0.5-V supply. The fabricated FBB mixer, comprising two asymmetrical broadside-coupled baluns, and all of test pads and dummy blocks, occupies an area of 0.72 mm2. An FOMDown-M2 that is obtained using the ultra-low power consumption FBB mixer is as high as 39.1.

關鍵字(中)

★ 非對稱式堆疊耦合架構之馬遜巴倫
★ 電流再生架構
★ 基體偏壓控制技術
★ 射頻收發機前端電路
★ 源極注入式混頻器
★ 超低功率消耗
★ 超低電壓
★ 升降頻
★ V-頻段
★ 90 奈米互補式金屬氧化物半導體製程

關鍵字(英)

★ Asymmetrical broadside-coupled balun
★ current-reused topology
★ forward body-biased (FBB) technique
★ RF transceiver front-end
★ source-driven mixer
★ ultra-low power
★ ultra-low voltage
★ up/down-conversion
★ V-band
★ 90 nm CMOS

論文目次

中文摘要....................................................I
Abstract.................................................III
誌謝 Acknowledgement......................................V
圖目錄 List of Figures.....................................IX
表目錄 List of Tables....................................XIII
Chapter 1 Introduction...............................1
1. 1 V-Band Unlicensed Spectrum.........................1
1. 2 V-Band Applications................................2
1. 3 Motivation of this Thesis..........................4
1. 4 Contributions......................................7
1. 5 Organization of this Thesis........................8
Chapter 2 Literature Review..........................9
2. 1 Recently Reported Baluns...........................9
2. 2 Recently Presented Passive Mixers.................10
2. 3 Recently Published Active Mixers..................13
Chapter 3 A Source-Driven Up-Conversion Mixer with Current-Reused Topology...................................16
3. 1 Conventional Mixer Topology.......................17
3. 2 The Proposed Up-Conversion Mixer..................21
3. 3 Measurement Results...............................26
3. 4 Summary...........................................32
Chapter 4 A Down-Conversion Mixer with Asymmetrical Marchand-Type Balun.......................................34
4. 1. The Asymmetrical Broadside-Coupled Balun..........34
4. 2. Implementation Results of the Designed Balun......46
4. 3. The Proposed Down-Conversion Mixer................49
4. 4. Measurement Results...............................58
4. 5. Summary...........................................65
Chapter 5 Conclusion and Future Works...............67
Bibliography..............................................70
Publications..............................................79

參考文獻

[1] WirelessHD. [Online]. Available: http://www.wirelesshd.org
[2] R.C. Daniels and R.W. Heath, "60 GHz wireless communications: emerging requirements and design recommendations," IEEE Vehicular Technology Magazine, vol.2, no.3, pp.41-50, Sept. 2007.
[3] N. Flaherty, "Hi-def goes wireless - [comms wireless HD]," Engineering & Technology, vol.3, no.15, pp.74,75, Sept. 2008.
[4] P. Smulders, "Exploiting the 60 GHz band for local wireless multimedia access: prospects and future directions," IEEE Commun. Mag., vol.40, no.1, pp.140-147, Jan. 2002.
[5] A. Maltsev, R. Maslennikov, A. Sevastyanov, A. Khoryaev, and A. Lomayev, "Experimental investigations of 60 GHz wireless systems in office environment, " IEEE J. Select. Areas Commun., vol. 27, no. 8, Oct. 2009.
[6] Wireless Gigabit Alliance. [Online]. Available: http://wirelessgigabitalliance.org/
[7] IEEE 802.11 Working Group. Very high throughput in 60 GHz. [Online]. Available: http://www.ieee802.org/11/Reports/tgad_update.htm
[8] S.K. Reynolds, B.A. Floyd, U.R. Pfeiffer, T. Beukema, J. Grzyb, C. Haymes, B. Gaucher, and M. Soyuer, "A silicon 60-GHz receiver and transmitter chipset for broadband communications," IEEE J. Solid-State Circuits, vol.41, no.12, pp.2820-2831, Dec. 2006.
[9] D.A. Sobel and R.W. Brodersen, "A 1Gbps mixed-signal analog front end for a 60GHz wireless receiver," in Proc. IEEE Symp. VLSI Circuits, June 2008, pp.156-157.
[10] A. M. Niknejad and H. Hashemi, Eds., mm-Wave Silicon Technology: 60 GHz and Beyond, Springer, 2008.
[11] A.M. Niknejad, "Siliconization of 60 GHz," IEEE Microw. Mag., vol.11, no.1, pp.78-85, Feb. 2010.
[12] A. Maltsev, R. Maslennikov, A. Sevastyanov, A. Khoryaev, and A. Lomayev, "Experimental investigations of 60 GHz WLAN systems in office environment," IEEE J. Select. Areas Commun., vol.27, no.8, pp.1488-1499, Oct. 2009.
[13] S.K. Reynolds, B.A. Floyd, U.R. Pfeiffer, T. Beukema, J. Grzyb, C. Haymes, B. Gaucher, and M. Soyuer, "A Silicon 60-GHz receiver and transmitter chipset for broadband communications," IEEE J. Solid-State Circuits, vol.41, no.12, pp.2820-2831, Dec. 2006.
[14] S.E. Gunnarsson, C. Karnfelt, H. Zirath, R. Kozhuharov, D. Kuylenstierna, A. Alping, and C. Fager, "Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology," IEEE J. Solid-State Circuits, vol.40, no.11, pp. 2174-2186, Nov. 2005.
[15] A. Natarajan, A. Komijani, G. Xiang, A. Babakhani, and A. Hajimiri, "A 77-GHz phased-array transceiver with on-chip antennas in silicon: transmitter and local LO-path phase shifting," IEEE J. Solid-State Circuits, vol.41, no.12, pp.2807-2819, Dec. 2006.
[16] M. Tiebout, H. Wohlmuth, H. Knapp, R. Salerno, M. Druml, M. Rest, J. Kaeferboeck, J. Wuertele, S.S. Ahmed, A. Schiessl, R. Juenemann, and A. Zielska, "Low power wideband receiver and transmitter chipset for mm-wave imaging in SiGe bipolar technology," IEEE J. Solid-State Circuits, vol.47, no.5, pp.1175-1184, May 2012.
[17] A.C. Heiberg, T.W. Brown, T.S. Fiez, K. Mayaram, "A 250 mV, 352 W GPS receiver RF front-end in 130 nm CMOS," IEEE J. Solid-State Circuits, vol.46, no.4, pp.938-949, Apr. 2011.
[18] A. Parsa and B. Razavi, "A new transceiver architecture for the 60-GHz band," IEEE J. Solid-State Circuits, vol.44, no.3, pp.751-762, Mar. 2009.
[19] J. Lee, Y. Chen, and Y.-L. Huang, "A low-power low-cost fully-integrated 60-GHz transceiver system with OOK modulation and on-board antenna assembly," IEEE J. Solid-State Circuits, vol.45, no.2, pp.264-275, Feb. 2010.
[20] D. Dawn, P. Sen, S. Sarkar, B. Perumana, S. Pinel, and J. Laskar, "60-GHz integrated transmitter development in 90-nm CMOS," IEEE Trans. Microwave Theory Tech., vol.57, no.10, pp.2354-2367, Oct. 2009.
[21] B. Razavi, RF and Microelectronics (2nd Edition). Upper Saddle River, NJ: Prentice-Hall, Oct. 2011.
[22] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001, ch. 2, pp. 13-28.
[23] H.-J. Wei, C.-C. Meng, T.-W. Wang, T.-L. Lo, and C.-L. Wang, "60-GHz dual-conversion Down-/Up-Converters Using Schottky Diode in 0.18-m Foundry CMOS technology," IEEE Trans. Microwave Theory Tech., vol.60, no.6, pp.1684-1698, June 2012.
[24] P.-C. Huang, R.-C. Liu, J.-H. Tsai, H.-Y. Chang, H. Wang, J. Yeh, C.-Y. Lee, and J. Chern, "A compact 35-65 GHz up-conversion mixer with integrated broadband transformers in 0.18-m SiGe BiCMOS technology," in IEEE Radio Frequency Integrated Circuits (RFIC) Symp., June 2006. pp., 11-13.
[25] F. Zhang, E. Skafidas, and W. Shieh, "60 GHz double-balanced up-conversion mixer on 130 nm CMOS technology," Electronics Lett., vol.44, no.10, pp.633-634, May 8 2008.
[26] I.C.H. Lai, Y. Kambayashi, M. Fujishima, "50 GHz double-balanced up-conversion mixer using CMOS 90 nm process," in Proc. IEEE Int. Symp. Circuits Syst., May 2007, pp.2542-2545.
[27] J.-H. Tsai, "Design of 40–108-GHz low-power and high-speed CMOS up-/down-conversion ring mixers for multistandard MMW radio applications," IEEE Trans. Microwave Theory Tech., vol.60, no.3, pp.670-678, Mar. 2012.
[28] R. Mongia, I. Bahl, and P. Bhartia, RF and Microwave Coupled-Line Circuits. Norwod, MA: Artech House, 1999.
[29] J.-X. Liu, C.-Y. Hsu, H.-R. Chuang, and C.-Y. Chen, "A 60-GHz millimeter-wave CMOS marchand balun," in IEEE Radio Frequency Integrated Circuits (RFIC) Symp., June 2007, pp.445-448.
[30] C.-C. Kuo, C.-L. Kuo, C.-J. Kuo, S.A. Maas, and H. Wang, "Novel miniature and broadband millimeter-wave monolithic star mixers," IEEE Trans. Microwave Theory Tech., vol.56, no.4, pp.793-802, Apr. 2008.
[31] M.-J. Chiang, H.-S. Wu, and C.-K. C. Tzuang, "A compact CMOS marchand balun incorporating meandered multilayer edge-coupled transmission lines," in IEEE MTT-S Int. Microwave Symp. Dig., June 2009, pp.125-128.
[32] D.A.A. Mat, R.K. Pokharel, R. Sapawi, H. Kanaya, and K. Yoshida, "60GHz-band on-chip Marchand balun designed on flat and patterned ground shields for milimeter-wave 0.18-m CMOS technology," in Proc. 2011 Asia-Pacific Microw. Conf., 5-8 Dec. 2011, pp.884-887.
[33] H.-K. Chiou and T.-Y. Yang, "Low-loss and broadband asymmetrical broadside-coupled balun for mixer design in 0.18-m CMOS technology," IEEE Trans. Microwave Theory Tech., vol.56, no.4, pp.835-848, Apr. 2008.
[34] H.-K. Chiou and J.-Y. Lin, "Symmetric offset stack balun in standard 0.13-m CMOS technology for three broadband and low-loss balanced passive mixer designs," IEEE Trans. Microwave Theory Tech., vol.59, no.6, pp.1529-1538, June 2011.
[35] Y. Sun and C.J. Scheytt, "A 122 GHz sub-harmonic mixer with a modified APDP topology for IC integration," IEEE Microw. Wireless Compo. Lett., vol.21, no.12, pp.679-681, Dec. 2011.
[36] H.-Y. Yang, J.-H. Tsai, C.-H. Wang, C.-S. Lin, W.-H. Lin, K.-Y. Lin, T.-W. Huang, and H. Wang, "Design and analysis of a 0.8–77.5-GHz ultra-broadband distributed drain mixer using 0.13-m CMOS technology," IEEE Trans. Microwave Theory Tech., vol.57, no.3, pp.562-572, Mar. 2009.
[37] F. Ellinger, L.C. Rodoni, G. Sialm, C. Kromer, B.G. Von, M.L. Schmatz, C. Menolfi, T. Toifl, T. Morf, M. Kossel, and H. Jackel, "30-40-GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology," IEEE Trans. Microwave Theory Tech., vol.52, no.5, pp.1382-1391, May 2004.
[38] F. Ellinger, "26.5–30-GHz resistive mixer in 90-nm VLSI SOI CMOS technology with high linearity for WLAN," IEEE Trans. Microwave Theory Tech., vol.53, no.8, pp.2559-2565, Aug. 2005.
[39] T.-Y. Yang and H.-K. Chiou, "A 16–46 GHz mixer using broadband multilayer balun in 0.18-μm CMOS technology," IEEE Microw. Wireless Compo. Lett., vol.17, no.7, pp.534-536, July 2007.
[40] H.-Y. Yang, J.-H. Tsai, T.-W. Huang, and H. Wang, "Analysis of a new 33–58-GHz doubly balanced drain mixer in 90-nm CMOS technology," IEEE Trans. Microwave Theory Tech., vol.60, no.4, pp.1057-1068, Apr. 2012.
[41] M. Parlak and J.F. Buckwalter, "A passive I/Q millimeter-wave mixer and switch in 45-nm CMOS SOI," IEEE Trans. Microwave Theory Tech., vol.61, no.3, pp.1131-1139, Mar. 2013.
[42] J.-H. Tsai and T.-W. Huang, "35–65-GHz CMOS broadband modulator and demodulator with sub-harmonic pumping for MMW wireless gigabit applications," IEEE Trans. Microwave Theory Tech., vol.55, no.10, pp.2075-2085, Oct. 2007.
[43] J.-H. Tsai, P.-S. Wu, C.-S. Lin, T.-W. Huang, J.G.J. Chern, and W.-C. Huang, "A 25–75 GHz broadband Gilbert-cell mixer using 90-nm CMOS technology," IEEE Microw. Wireless Compo. Lett., vol.17, no.4, pp.247-249, Apr. 2007.
[44] C.-Y. Wang and J.-H. Tsai, "A 51 to 65 GHz low-power bulk-driven mixer using 0.13-m CMOS technology," IEEE Microw. Wireless Compo. Lett., vol.19, no.8, pp.521-523, Aug. 2009.
[45] J.-H. Tsai, "Design of 1.2-V broadband high data-rate MMW CMOS I/Q modulator and demodulator Using presented Gilbert-cell mixer," IEEE Trans. Microwave Theory Tech., vol.59, no.5, pp.1350-1360, May 2011.
[46] J. Kim, K.T. Kornegay, J. Alvarado, C.-H. Lee, and J. Laskar, "W-band double-balanced down-conversion mixer with Marchand baluns in silicon-germanium technology," Electronics Lett., vol.45, no.16, pp.841-843, July 30 2009.
[47] J.-J. Kuo, C.-H. Lien, Z.-M. Tsai, K.-Y. Lin, K. Schmalz, J.C. Scheytt, and H. Wang, "Design and analysis of down-conversion gate/base-pumped harmonic mixers using novel reduced-size 180o hybrid with different input frequencies," IEEE Trans. Microwave Theory Tech., vol.60, no.8, pp.2473-2485, Aug. 2012.
[48] C.-H. Lien, P.-C. Huang, K.-Y. Kao, K.-Y. Lin, and H. Wang, "60 GHz double-balanced Gate-pumped down-conversion mixers with a combined hybrid on 130 nm CMOS processes," IEEE Microw. Wireless Compo. Lett., vol.20, no.3, pp.160-162, Mar. 2010.
[49] F. Zhang, B. Yang, E. Skafidas, and W. Shieh, "5-75 GHz common-gate subharmonic mixer in 65 nm CMOS," Electronics Lett., vol.46, no.17, pp.1203-1205, Aug. 2010.
[50] D.-H. Kim, S.-J. Kim, and J.-S. Rieh, "A 60 GHz wideband quadrature-balanced mixer based on 0.13-m RFCMOS technology," IEEE Microw. Wireless Compo. Lett., vol.21, no.4, pp.215-217, Apr. 2011.
[51] C.-W. Byeon, J.-J. Lee, I.-S. Song, and C.-S. Park, "A 60 GHz current-reuse LO-boosting mixer in 90 nm CMOS," IEEE Microw. Wireless Compo. Lett., vol.22, no.3, pp.135-137, Mar. 2012.
[52] N. Zhang, H. Xu, H.-T. Wu, and K.O. Kenneth, "W-Band active down-conversion mixer in bulk CMOS," IEEE Microw. Wireless Compo. Lett., vol.19, no.2, pp.98-100, Feb. 2009.
[53] H.-T. Chou, J.-R. Liang, H.-K. Chiou, "V-band low-power Darlington-pair gate-pumped mixer with thin-film LC-hybrid linear combiner in 90 nm CMOS," Electronics Lett., vol.48, no.16, pp.1023-1024, Aug. 2012.
[54] A.V. Do, C.C. Boon, A.V. Do, K.-S. Yeo, and A. Cabuk, "A weak-inversion low-power active mixer for 2.4 GHz ISM band applications," IEEE Microw. Wireless Compo. Lett., vol.19, no.11, pp.719-721, Nov. 2009.
[55] W.-T. Li, H.-Y. Yang, Y.-C. Chiang, J.-H. Tsai, M.-H. Wu, and T.-W. Huang, "A 453-W 53–70-GHz ultra-low-power double-balanced source-driven mixer using 90-nm CMOS technology," IEEE Trans. Microwave Theory Tech., vol.61, no.5, pp.1903-1912, May 2013.
[56] Sedra and Smith, “Microelectronic Circuits 4th ed.,” Oxford, U.K., Oxford Univ., 2006.
[57] C. Andrei, D. Gloria, F. Danneville, and G. Dambrine, "Efficient de-embedding technique for 110-GHz deep-channel-MOSFET characterization," IEEE Microw. Wireless Compo. Lett., vol. 17, no. 4, pp. 301-303, Apr. 2007.
[58] H. Cho, and D. E. Burk, "A three-step method for the de-embedding of high-frequency S-parameter measurements," IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1371-1375, June 1991.
[59] E. P. Vandamme, et.al, "Improved three-step de-embedding method to accurately account for influence of pad parasitics in silicon on-wafer RF test-structures," IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 737-742, Apr. 2001.
[60] T. E. Kolding, "A four-step method for de-embedding gigahertz on-wafer CMOS measurements," IEEE Trans. Electron Devices, vol. 47, no. 4, pp. 734–740, Apr. 2000.
[61] C. H. Chen and M. J. Deen, "A general noise and S-parameter de-embedding procedure for on-wafer high-frequency noise measurements of MOSFETs," IEEE Trans. Microw. Theory Tech., vol. 49, no. 5, pp. 1004-1004, May 2001.
[62] L. F. Tiemeijer, R. J. Havens, A. B. M. Jansman, and Y. Bouttement, "Comparison of the ‘pad-open-short’ and ‘open-short-load’ de-embedding techniques for accurate on-wafer RF characterization of high quality passives, " IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 723-729, Feb. 2005.
[63] J.R. Long, "Monolithic transformers for silicon RF IC design," IEEE J. Solid-State Circuits, vol.35, no.9, pp.1368-1382, Sept. 2000.
[64] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998.
[65] G. E. Ponchak and A.N. Downey, "Characterization of thin film microstrip lines on polyimide," IEEE Trans. Comp., Packag., Manufact. Technol. B, vol.21, no.2, pp.171-176, May 1998.
[66] H.-W. Wu, M.-H. Weng, Y.-K. Su, R.-Y. Yang, and C.-Y. Hung, "Equivalent lumped elements of DC-biased thin film microstrip line in MMICs," IEEE Microw. Wireless Compo. Lett., vol.17, no.9, pp.673-675, Sept. 2007.
[67] G. Six, G. Prigent, E. Rius, G. Dambrine, and H. Happy, "Fabrication and characterization of low-loss TFMS on silicon substrate up to 220 GHz," IEEE Trans. Microw. Theory Tech., vol.53, no.1, pp.301-305, Jan. 2005.
[68] F. Schnieder and W. Heinrich, "Model of thin-film microstrip line for circuit design," IEEE Trans. Microw. Theory Tech., vol.49, no.1, pp.104-110, Jan. 2001.
[69] J. Gondermann, E.G.S. von Kamienski, H.G. Roskos, and H. Kurz,, "Al-SiO2-Al sandwich microstrip lines for high-frequency on-chip interconnects," IEEE Trans. Microw. Theory Tech., vol.41, no.12, pp.2087-2091, Dec. 1993.
[70] Y. Wang, J.S. Duster, K.T. Kornegay, P. Hyun-min, and J. Laskar, "An 18GHz low noise high linearity active mixer in SiGe," in Proc. IEEE Int. Symp. Circuits Syst., May 2005, Vol. 4 ,pp. 3243-3246.
[71] H.-K. Chiou and H.-T. Chou, "A 0.4 V microwatt power consumption current-reused up-conversion mixer," IEEE Microw. Wireless Compo. Lett., vol.23, no.1, pp.40-42, Jan. 2013.

指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2013-8-14

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