博碩士論文 985401024 詳細資訊




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姓名 黃健智(Chien-Chih Huang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於交換電容式類比電路之馴變電容佈局擺置方法
(Variation-Aware Placement of Common-Centroid Unit Capacitor Array for Switched-Capacitor Analog Circuits)
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摘要(中) 電容比值廣泛應用於類比電路設計,例如:切換式電容積分器、類比/數位轉換器。隨著半導體製程的演進,電容比值的精確度受製程系統性變異與隨機性變異的影響越來越大。由並聯單位電容所組成的電容陣列能有效地抑制製程變異造成的電容比值不匹配,並進而延伸出單位電容佈局問題。本論文的貢獻在於連結電容佈局與電容比值變異的關係,並進而提出分割式演算法於電容陣列佈局。本論文證明給定一個電容佈局範圍時,把單位電容擺置於佈局範圍的中心位置時,將能獲得最小的比值變異。運用這個特徵,較大的佈局範圍切割成數個較小的佈局範圍,並為每個切割範圍的中心位置上擺置單位電容,其所產生的佈局不僅快速且擁有共質心、對稱性與均勻分散等佈局法則。最後,當把這項技術運用在二元權重式電容陣列佈局,例如:逐漸趨近式類比數位轉換器,實驗顯示,本論文所提出的二元權重式電容佈局在二元比值變異、電路線性程度效能、佈局產生的時間均明顯優於現階段已提出之電容佈局。
摘要(英) The key performance of many analog integrated circuits, such as switched-capacitor integrator and analog-to-digital converter, are directly related to their accurate capacitance ratios. The accuracy of capacitance ratio is affected by the systematic and random variations of manufacturing processes more significantly when the manufacturing processes continue to shrink. The variation of capacitance ratio, which can be alleviated by paralleling unit capacitors, is then extended to the capacitor array placement problem. This dissertation is devoted to establish the relationship between the capacitor array placement and the capacitance ratio variation, and to propose the partition-based algorithm to form the capacitor array placement. Placing a unit capacitor at the center of a partitioned sub-array can achieve the lowest variations both systematic and random will be proved. Based on the approach to placing unit capacitor at the center of partitioned sub-array, the capacitor array placement is effectively generated and satisfied the coincidence, symmetry, and dispersion rules. Finally, the proposed algorithm is further applied to the placement of a binary-weighted capacitor array, which is used in successive-approximation register (SAR) analog-to-digital converters (ADCs). Experimental results show that the binary-weighted capacitor array placement can achieve less variation on binary-weighted continued ratio, higher linearity performance, and shorter placement generation time than the state-of-the-art.
關鍵字(中) ★ 類比電路佈局
★ 電容比值匹配
★ 空間相關性係數
★ 單位電容佈局
★ 二元權重電容佈局
關鍵字(英) ★ Analog placement
★ capacitance ratio mismatch
★ spatial correlation coefficient
★ unit capacitor array placement
★ successive-approximation-register ADC
★ binary-weighted continued ratio
論文目次 Chapter 1 Introduction 1
1.1 Capacitor Array Placement Problem 3
1.2 Contributions and Significance 6
1.3 Organization of Dissertation 7
Chapter 2 Preliminaries 8
2.1 Oxide-Gradient-Induced Model of Systematic Mismatch 8
2.2 Spatial Correlation Coefficient Model of Random Mismatch 11
Chapter 3 Capacitor Array Placement Methodology 17
3.1 Heuristic Capacitor Placement Algorithm 18
3.2 Pair-Sequence Simulated Annealing Capacitor Placement Algorithm 22
3.3 Summary 26
Chapter 4 Variance-Aware Capacitor Array Placement 28
4.1 Counter-Example on Criteria ρCi,j 29
4.2 Variance-Aware Criteria 31
4.3 Capacitor Array Placement of Variance Optimum 35
4.3.1 Optimal Variance C-entry Placement 40
4.4 Partitioning and Merging Placement Methodology 41
4.4.1 Partitioning Scheme 41
4.4.2 Merging Scheme 44
Chapter 5 Capacitor Array Placement on Continued Ratio 47
5.1 Criteria on Overall Correlation Coefficient L 48
5.2 Operation of SAR ADCs and Binary-Weighted Continued Ratio 52
5.3 Optimization Criterion on Binary-Weighted Continued Ratio 55
5.3.1 Optimization Criteria on Overall Correlation Coefficient L 55
5.3.2 Optimization Criteria on Ratio Mismatch M 57
5.3.3 Criterion on Parasitic Capacitances and Layout 59
5.4 Performance Metric of Binary-Weighted Continued Ratio 62
5.4.1 Linear Ramp Histogram Method 62
5.4.2 Performance Metric on Random Mismatch 63
5.4.3 Performance Metric on Systematic Mismatch 66
5.5 PACES Placement Algorithm for Binary-Weighted Continued Ratio 70
5.6 Experimental Results 75
Chapter 6 Conclusions and Future Works 81
6.1 Contributions 81
6.2 Future Works 82
References 85
參考文獻 [1] P. M. Aziz and H. V. Sorensen, “An Overview of Sigma-Delta Converters,” IEEE Signal Processing Magazine, vol. 68, no. 1, pp. 61-84, Jan. 1996.
[2] L. Yao, "A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90-nm MOS," IEEE Journal of Solid-State Circuits, vol. 39, no. 11, pp. 1809-1818, Nov. 2004.
[3] P.-W. Luo, "Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits," Ph.D. dissertation, Department of Electrical Engineering, National Central University, Taiwan, 2011.
[4] M. Pelgrom, A. Duimnaijer, and A. Welbers, “Matching Properties of MOS Transistors,” IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433-1440, Oct. 1989.
[5] S. W. Director, P. Feldmann and K. Krishna, “Statistical Integrated Circuit Design,” IEEE Journal of Solid-State Circuits, vol. 28, no. 3, pp. 193-202, Mar. 1993.
[6] M. J. Mcnutt, S. Lemarquis, and J. L. Dunkly, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE Journal of Solid-State Circuits, vol. 29, no. 5, pp. 611-616, May. 1994.
[7] A. Hastings, The Art of Analog Layout, Prentice Hall, 2000.
[8] H. Masuda, S. Ohkawa, A. Kurokawa, and M. Aoki, “Challenge: Variability Characterization and Modeling for 65- to 90-nm Processes,” in Proc. of the IEEE Custom Integrated Circuits Conference, pp. 593-599, 2005.
[9] J. Liu, S. Dong, X. Hong, Y. Wang, O. He, and S. Goto, “Symmetry Constraint Based on Mismatch Analysis for Analog Layout in SOI Technology,” in Proc. of the Asia and South Pacific Design Automation Conference, pp. 772–775, 2008.
[10] C. Cho, D. Kim, J. Kim J.-O. Plouchart and R. Trzcinski, “Statistical Framework for Technology-Model-Product Co-Design and Covergence,” in Proc. of the Design Automation Conference, pp. 503-508, 2007.
[11] F. Liu, “A General Framework for Spatial Correlation Modeling in VLSI Design,” in Proc. of the Design Automation Conference, pp. 817-822, 2007.
[12] X. Jinjun, V. Zolotov, and H. Lei, “Robust Extraction of Spatial Correlation,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, pp. 619-631, Apr. 2007.
[13] J. Luo, S. Sinha, Q. Su, J. Kawa and C. Chiang, “An IC Manufacturing Yield Model Considering Intra-Die Variations,” in Proc. of the Design Automation Conference, pp. 749-754, 2006.
[14] B. E. Stine, D. S. Boning and J. E. Chung, “Analysis and Decomposition of Spatial Variation in Integrated Circuit Processes and Devices,” IEEE Transactions on Semiconductor Manufacturing, vol. 10, no. 1, pp. 24-41, Feb. 1997.
[15] D. Sayed and M. Dessouky, “Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio,” in Proc. of the Conference on Design, Automation and Test in Europe, pp. 576–580, Mar. 2002.
[16] D. Khalil, M. Dessouky, V. Bourguet, M.-M. Louerat, A. Cathelin and H. Ragai, “Compensated Layout for Automated Accurate Common-Centroid Capacitor Arrays,” in Proc. of IEEE Int. Conf. Elect. Electron. Comput. Eng., pp. 481-484, Sep. 2004.
[17] D. Khalil, M. Dessouky, V. Bourguet, M. M. Louerat, A.Catheline, and H. Ragai, “Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays,” in Proc. of International Symposiums on Quality of Electronic Design, pp. 143–147, 2005.
[18] X. Dai, C. He, H. Xing, D. Chen, and R. L. Geiger, “An Nth Order Central Symmetrical Layout Pattern for Nonlinear Gradient Cancellation,” IEEE International Symposiums on Circuits and Systems, pp. 4835-4838, 2005.
[19] Q. Ma, F. Y. Young, and K. P. Pun, “Analog Placement with Common Centroid Constraints,” IEEE/ACM International Conference on Computer-Aided Design, pp. 579-85, 2007.
[20] P.-W. Luo, J.-E. Chen, C. L. Wey, L.-C. Cheng, J.-J. Chen, and W.-C. Wu, “Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 11, pp. 2097-2101, Nov. 2008.
[21] J.-E. Chen, P.-W. Luo, and C. L. Wey, “Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 2, pp. 313-318, Feb. 2010.
[22] P.-W. Luo, J.-E. Chen, M.-Y. Huang, and C. L. Wey, “Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E94-A, no. 1, pp. 352-361, Jan. 2011.
[23] H. E. Graeb, Analog Design Centering and Sizing, Springer, 2007.
[24] Y. F. Huang, “Iterative Optimization of Spatial Correlation for Switch-Capacitor Delta-Sigma Modulator,” master’s thesis, Dept. Electrical Engineering, Chung-Hua University, Hsinchu, 2006.
[25] C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang, and S.-J. Chang, “Common-Centroid Capacitor Placement Considering Systematic and Random Mismatches in Analog Integrated Circuits,” in Proc. of the Design Automation Conference, pp. 528-533, 2011.
[26] C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang, and S.-J. Chang, “Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 12, pp. 1789-1802, Dec. 2012.
[27] M. P.-H. Lin, Y.-T. He, W.-H. Hsiao, R.-G. Chang, and S.-Y. Lee, “Common-Centroid Capacitor Layout Generation Considering Device Matching and Parasitic Minimization,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 7, pp. 991-1002, Jul. 2013.
[28] M. P.-H. Lin, V. W.-H. Hsiao and C.-Y. Lin, “Parasitic-aware Sizing and Detailed Routing for Binary-Weighted Capacitors in Charge-scaling DAC,” in Proc. of the Design Automation Conference, pp. 1-6, Jun. 2014.
[29] K.-H. Ho, H.-C. Ou, Y.-W. Chang and Hui-Fang Tsao, "Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 2, pp. 161-172, Feb. 2015.
[30] Y. Li, Z. Zhang, D. Chua, and Y. Lian. 2014. “Placement for Binary-Weighted Capacitive Array in SAR ADC Using Multiple Weighting Methods,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 9, pp. 1277-1286, Sep. 2014.
[31] C.-C. Huang, C. L. Wey, J.-E. Chen, and P.-W. Luo, “Optimal Common-Centroid-Based Unit Capacitor Placements for Yield Enhancement of Switched-Capacitor Circuits,” ACM Trans. on Design Automation of Electronics Systems, vol. 19, no. 1, Dec. 2013.
[32] C.-C. Huang, C. L. Wey, J.-E Chen, and P.-W. Luo, “Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs,” ACM Trans. on Design Automation of Electronics Systems, accepted to be appeared, May 2015.
[33] R. E. Walpole, R. H. Myers, S. L. Myers and K. Ye, Probability and Statistics for Engineers and Scientists, Prentice Hall, 2011.
[34] A. Stuart and J. K. Ord, Kendall’s Advanced Theory of Statistics, Wiley, 1987.
[35] G. Casella and R. L. Berger, Statistical Inference, Duxbury Press, 2001.
[36] D. Johns and K. Marti, Analog Integrated Circuit Design, Wiley, 1997.
[37] S. Haenzsche, S. Henker, and R. Schuffny, “Modeling of Capacitor Mismatch and Non-Linearity Effects in Charge Redistribution SAR ADCs,” in Proc. of the International Conference Mixed Design of Integrated Circuits and Systems, pp. 300-305, 2010.
[38] Y.-Z Lin, C.-C Liu, G.-Y. Huang, Y.-T. Shyu, Y.-T Liu, and S.-J. Chang, “A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS,” IEEE Trans. on Circuits and Systems, vol. 60, no. 3, pp. 570-581, Mar. 2013.
[39] M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement, Oxford, 2001.
指導教授 陳竹一、魏慶隆(Jwu-E Chen Chin-Long Wey) 審核日期 2016-1-18
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