博碩士論文 992212008 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:9 、訪客IP:3.219.167.194
姓名 李昇龍(Sheng-Long Li)  查詢紙本館藏   畢業系所 照明與顯示科技研究所
論文名稱 具45°矽微反射面SOI波導之5-Gbps晶片內光學連接收發模組
(Intra-Chip 5-Gbps Optical Interconnect Module Using SOI-Based Waveguides with Silicon 45° Micro-Reflectors)
相關論文
★ 具平坦化側帶之超窄帶波導模態共振濾波器研究★ 以矽光學平台為基礎之4通道×10-Gbps 光學連結模組之接收端研究
★ 透明導電層上之高分子聚合物微奈米光學結構於氮化鎵發光二極體光學特性研究★ 具45度反射面之非共平面轉折波導光路
★ 以矽光學平台為基礎之4通道 x 10 Gbps光學連結模組之發射端★ 具三維光路之光連接發射端模組
★ 矽基光學平台技術為核心之雙向4通道 x 10-Gbps光學連接收發模組★ 建立於矽基光學平台之高分子聚合物波導光路
★ 適用於色序式微型投影機之微透鏡陣列積分器光學系統研製★ 發光二極體色溫控制技術及其於色序式微型投影機之應用
★ 具45˚矽基反射面高分子聚合物波導之10-Gbps晶片內部光學連接收發模★ 在陶瓷基板實現高速穿孔架構之5-Gbps光學連接模組
★ 具垂直分岔光路之10-Gbps雙輸出矽基光學連接模組★ 利用光展量概念之微型投影機光學設計方法與實作
★ 以1 × 2垂直分岔高分子聚合物光路實現單晶片20-Gbps矽基光學連接模組★ 利用三維矽波導光路實現10-Gbps單晶片光學連接模組
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 ( 永不開放)
摘要(中) 在本論文中,將提出一個建構於SOI基板上並與45°矽微反射面和矽波導整合之5-Gbps光學連接模組。此模組中,45°微反射面的建構是利用具等向性的濕蝕刻製程,於(100)晶向面的SOI晶圓之光子元件層上製作。其中,面射型雷射陣列和光偵測器陣列封裝於SOI晶圓之矽基板層的上面。而透過一次微影蝕刻的手法將45°微反射面與波導整合在SOI晶圓上,將可實現三維光路的建構。此三維光路首先由面射型雷射發射雷射光,透過45°微反射面耦合進波導中,再由另一個45°矽微反射面將光反射至光偵測器。
根據光學模擬結果顯示,本論文設計出之模組的光學效率可達67.4 %,而經由實際量測製程出來之模組,本模組的光學效率可達67 %。而且雷射和光偵測器在光學效率為1 dB時的位移容忍度皆可大於24 μm。證實了本論文所設計之光學平台可適用於雷射和光偵測器等主動元件的整合。
在模組的高頻傳輸能力上,本模組在未加接收端驅動IC之情況下,供給10 mA之電流源於面射型雷射並操作在5 Gbps的傳輸速率時,眼圖眼高為28.8 mV、抖動為25.51 ps、訊雜比可達8.1,而且眼圖訊號在其眼睛邊際 (Eye margin) 內是非常乾淨。本模組在加入接收端驅動IC後,眼圖的表現會有劇烈的提升。同樣供給10 mA之電流源於面射型雷射並操作在5 Gbps的傳輸速率時,眼圖眼高為228 mV、訊雜比可達13.81,其訊號之清晰程度有明顯的增加,而抖動為40.21 ps仍適用於5-Gbps的傳輸速率。而經過誤碼率的量測顯示,當雷射之驅動電流降至4 mA時,誤碼率仍能小於10-12等級。因此證明了本模組在5 Gbps的傳輸速率時具有較低的功耗。
摘要(英) In this thesis, we proposed an intra-chip 5-Gbps optical interconnect module based on a silicon-on-insulator (SOI)-based substrate with silicon waveguides terminated with 45° micro-reflectors. The 45° slants of proposed waveguide are fabricated on the device layer of (100)-oriented SOI wafer using anisotropic wet etching. The vertical-cavity-surface-emitted-laser (VCSEL) array and the photo-detector (PD) array are assembled on the substrate layer of SOI wafer. The three-dimensional guide-wave path is realized by the 45° micro-reflectors monolithically integrated on the silicon waveguide. The laser beam emitting from the VCSEL array is coupled into the waveguide via a 45° micro-reflector, propagates along the waveguide, and then is coupled into the PD via another 45° micro-reflector at the output port.
According to the optical simulated and experiment results, the optical efficiency along the VCSEL-waveguide-PD path of proposed module is 67%. Its 1-dB alignment tolerance of assembling a VCSEL or PD chip is as larger as 24 μm. It demonstrates that the optical characteristics of proposed guide-wave configuration on SOI wafer would facilitate the assembly of active devices.
The high-frequency modulation of active devices is also studied at the fabricated modules. As the VCSEL array is biased at 10 mA, without an amplifier IC at the receiver side, the clear eye diagram with a eye height of 28.8 mV, a jitter of 25.51 ps, and the signal-to-noise ratio of 8.1 is demonstrated at the data rate of 5 Gbps. With the assistance of amplifier IC at the receiver side, the performance of eye diagram can be improved dramatically. Its eye height of 282 mV and the signal-to-noise ratio of 13.81 are demonstrated at the same biased condition of 10 mA. A jitter of 40.21 ps suitable for the data rate of 5 Gbps is obtained at such improved eye height. The 5-Gbps error-free performance of receiver side is also achieved at the level of 10-12 even the VCSEL is biased at 4 mA. The experiment data verifies the proposed intra-chip module can be operated at 5 Gbps with a low power consumption.
關鍵字(中) ★ SOI波導
★ 光學連接模組
關鍵字(英) ★ Optical Interconnect
★ Intra-Chip
論文目次 摘要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 viii
第一章 緒論 1
1-1 研究動機 1
1-2 晶片內光學連接技術之發展現況 5
1-3 晶片內光連接收發模組的設計 8
第二章 模組設計 10
2-1 面射型雷射和光偵測器之光電特性的量測 11
2-1-1 面射型雷射之架構和規格以及光電特性的量測 11
2-1-2 光偵測器之架構和規格以及光電特性的量測 13
2-2 SOI 基板之結構設計 15
2-2-1 絕緣層厚度 (Isolation Layer) 的設計 15
2-2-2 矽基板層 (Substrate Layer) 阻值與厚度的設計 16
2-2-3 緩衝層 (BOX Layer) 厚度的設計 17
2-2-4 光子元件層 (Device Layer) 的設計 19
2-2-5 硬遮罩層 (Hard Mask Layer) 的設計 19
2-3 導波光波導之結構設計 20
2-3-1 45°微反射面與梯形脊狀波導的建構 20
2-3-2 模組光學分析 21
2-3-3 不同波導尺寸的光學模擬分析 22
2-3-4 以光線追跡法模擬此光路的合理性 25
2-4 高頻傳輸線之結構設計 26
2-4-1 高頻傳輸線之物理分析 26
2-4-2 高頻傳輸線損耗之數值分析方法 27
2-4-3 數位訊號的物理分析 28
2-4-4 本模組高頻傳輸線的設計 29
2-4-5 高頻傳輸線的模擬結果 30
第三章 製程開發 32
3-1 導波光波導的製作 32
3-2 化學機械研磨製程以及二氧化氣薄膜之沉積 35
3-2-1 化學機械研磨製程 35
3-2-2 二氧化矽薄膜沉積製程 36
3-3 高頻傳輸線與錫金焊料的製作 38
3-4 面射型雷射與光偵測器之覆晶片封裝製程 40
第四章 模組之高頻特性量測 41
4-1 傳輸線散射參數的量測 41
4-2 模組之高頻特性量測 43
4-2-1 眼圖的品質分析 43
4-2-2 模組頻率響應的量測 45
4-2-3 模組光學效率以及I-V曲線的量測 47
4-2-4 模組眼圖的量測 48
4-3 模組與接收端驅動IC整合之高頻特性量測 52
4-3-1 加入接收端驅動IC之模組介紹 52
4-3-2 接收端驅動IC之簡介 53
4-3-3 加入接收端驅動IC之模組眼圖量測 53
第五章 結論與未來展望 57
參考文獻 59
參考文獻 [1] S. Hiramatsu and T. Mikawa, “Optical design of active interposer for high-speed chip level optical interconnects,” IEEE J. Sel. Top. Quantum Electron., 24(2), 927-934 (2006).
[2] M. Aljada, K. E. Alameh, Y. T. Lee, and I. S. Chung, “High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors,” Opt. Express, 14(15), 6823-6836 (2006).
[3] X. Wang and R. T. Chen, “Fully embedded board level optical interconnects — From point-to-point interconnection to optical bus architecture,” Proc. SPIE, 6899, 6899031-6899039 (2008).
[4] J. A. Davis, R Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahamn, R. Reif, and J. D. Meindl, “Interconnect Limits on Gigascal Intergration (GSI) in the 21st Century” Proc. IEEE Micro, vol. 89, pp. 305-324, (2001)
[5] David A. B. Miller and H. M. Ozaktas, “Limit to the Bit-Rate Capacity of Electrical Interconnects from the Aspect Ratio of the System Architecture” J. Parallel Distrib. Comput., vol. 41, p. 4252, 1997
[6] K. C. Sarawat and F. Mohammadi, “Effect of Scaling of Interconnections on the Time Delay of VLSI Circuit” IEEE Trans. Electron Devices, vol. ED-29, no. 4,pp. 645-650 (1982)
[7] David M. Pozer “Microwave Engineering” John Wiley & Sons, Inc. 2005
[8] M. Haurylau, C. Q. Chen, H. Chen, J. D. Zhang, N. A. Nelson, D. H. Albonesi, E. G. Friedman, and P. M. Fauchet, “On-chip Optical Interconnect Roadmap: Challenges and Critical Directions” IEEE J. Sel. Topics Quantum Electron., vol. 12, no. 6,pp. 1699-1705, (2007)
[9] David A. B. Miller “Physical Reasons for Optical Interconnection,” Int. J. Optoelectronics 11,155-168 (1997)
[10] David A. B. Miller “Device Requirement for Optical Interconnects to Silicon Chips” IEEE (2009)
[11] L. Chen and M. Lipson, “Ultra-low capacitance and high speed germanium photodetectors on silicon,” Opt. Express 17(10), 7901-7906 (2009)
[12] L. Chen, K. Preston, S. Manipatruni, and M. Lipson, “Integrated GHz silicon photonic interconnect with micrometer-scale modulators and detectors,” Opt. Express 17(17), 15248-15256 (2009)
[13] J. V. Campenhout, P. R. A. Binetti, P. R. Romeo, P. Regreny, C. Seassal, X. J. M. Leijtens, T. de Vries, Y. S. Oei, R. P. J. van Veldhoven, R. Nötzel, L. Di Cioccio, J. M. Fedeli, M. K. Smit, D. Van Thourhout, and R. Baets, “Low-Footprint Optical Interconnect on an SOI Chip Through Heterogeneous Integration of InP-Based Microdisk Lasers and Microdetectors,” IEEE Photon. Technol. Lett. 21(8), 522-524 (2009)
[14] C. S. Lee, Thomas Frost, and Pallab Bhattacharya, CLEO Technical Digest, OSA, ( 2012)
[15] T. Spuesens, L. Liu, D.Vermeulen, J. Zhao, P. R. Romeo, P. Regreny, L. Genouillet, J.M. Fédeli, D. V. Thourhout, “Integration of photodetectors with lasers for optical interconnects using 200 mm waferscale III-V/SOI technology” JThA27, OSA/OFC/NFOEC (2011)
[16] B. Ciftcioglu, R. Berman, S. Wang, J. Hu, I. Savids, M. Jain, D. Moore, M. Huang, E. g. Friedman, G. Wicks and H. Wu, “3-D Integrated Heterogenoous Intra-Chip Free-Space Optical Interconnect” Opt. Express, vol. 20, No. 4 (2009)
[17] C. Gell, M. Berndt, J . Enderlein and S. Diez “TIRF Microscopy Evanescent Field Calibration Using Tilted Fluorescent Microtubules” Journal of Microscopy, Vol. 234, Pt 1 2009, pp. 38–46,( 2008)
[18] 沈帛寬,”具45°反射面之非共平面轉折波導光路,” (中央大學光電所碩士論文, 台灣, 2010)
[19] B. E. Lemoff, M. E. Ali, G. Panotopoulos, G. M. Flower, B. Mahdavan, A. F. J.Levi, and D. W. Dolfi, “MAUI: Enabling fiber-to-processor with parallel multiwavelength optical interconnects,” IEEE J. Lightwave Technol., 22, 2043-2054 (2004).
[20] F. Wang, F. Liu, and A. Adibi, “45 degree polymer micromirror integration for board-level three-dimensional optical interconnects,” Opt. Express, 17, 10514-10521 (2009).
[21] 張育誠, “微型光學讀取頭之元件,” (中央大學光電所碩士論文, 台灣, 2003)
[22] I. Zubel, “Silicon anisotropic etching in alkaline solutions III: On the possibility of spatial structures forming in the course of Si(100) anisotropic etching in KOH and KOH+IPA solutions,” Sensors and Actuators A: Physical, 84, p. 116-125 (2000)
[23] I. Zubel, “Silicon anisotropic etching in alkaline solutions IV – The effect of organic and inorganic agents on silicon nisotropic etching process,” Sensors and Actuators A: Physical, 87, p. 163-171 (2001)
[24] I. Zubel, “The effect of isopropyl alcohol on etching rate and roughness of (100) Si surface etched in KOH and TMAH solutions,” Sensors and Actuators A: Physical, 93, p. 138-147 (2001)
指導教授 伍茂仁(Mount-Learn Wu) 審核日期 2013-1-23
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明