以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：24

、訪客IP：3.144.30.70

姓名	沈帛寬(Po-kuan Shen)  查詢紙本館藏	畢業系所	光電科學與工程學系
論文名稱	三維光學網路於單晶片光學連接之研究 (Research on 3-D Network Optical Path for Chip-Level Optical Interconnect)
相關論文	★ 具平坦化側帶之超窄帶波導模態共振濾波器研究 ★ 以矽光學平台為基礎之4通道×10-Gbps 光學連結模組之接收端研究 ★ 透明導電層上之高分子聚合物微奈米光學結構於氮化鎵發光二極體光學特性研究 ★ 具45度反射面之非共平面轉折波導光路 ★ 以矽光學平台為基礎之4通道 x 10 Gbps光學連結模組之發射端 ★ 具三維光路之光連接發射端模組 ★ 矽基光學平台技術為核心之雙向4通道 x 10-Gbps光學連接收發模組 ★ 建立於矽基光學平台之高分子聚合物波導光路 ★ 適用於色序式微型投影機之微透鏡陣列積分器光學系統研製 ★ 發光二極體色溫控制技術及其於色序式微型投影機之應用 ★ 具45˚矽基反射面高分子聚合物波導之10-Gbps晶片內部光學連接收發模 ★ 在陶瓷基板實現高速穿孔架構之5-Gbps光學連接模組 ★ 具垂直分岔光路之10-Gbps雙輸出矽基光學連接模組 ★ 利用光展量概念之微型投影機光學設計方法與實作 ★ 以1 × 2垂直分岔高分子聚合物光路實現單晶片20-Gbps矽基光學連接模組 ★ 利用三維矽波導光路實現10-Gbps單晶片光學連接模組
檔案	[Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 (2025-4-2以後開放)
摘要(中)	在本論文中，主要研究在SOI基板上開發三維光學網路，並將其應用於晶片等級的光學連接模組。本研究可區分為三個主題：點對點的三維光路架構、具有垂直分光器或垂直轉換結構的三維光路網路、以及在SOI基板上實現具有雷射與光偵測器的晶片等級光連接模組。藉由三維光學網路的開發，光路與電路可利用相容的製程技術分別建構在SOI基板的正反兩側。此外經由獨特的光電分離架構，光電元件與光子元件可以非常容易地與電子元件整合在單一矽晶片上，並且實現高傳輸速度與低功耗的晶片等級光學連接模組。 在點對點的三維光路之研究上，我們利用非等向性的濕蝕刻技術，將高品質的45˚微反射面與單晶矽梯形波導建構在SOI基板的光學元件層。藉由三維光路的設計，我們可同時解決三項問題，包含光源與光偵測器的整合、低損耗的單晶矽波導、以及光電分離式的整合設計。經由量測結果得知，從入射端單模光纖到出射端多模光纖的光學傳輸效率約為-2.91 dB，長直光波導的傳播損耗約為0.404 dB/cm。同時我們也驗證光纖對於此三維光路的位移容忍度，其中入射端單模光纖對於光波導的位移容忍度可大於±5 μm；出射端多模光纖對於光波導的位移容忍度可大於±14 μm。如此寬鬆的位移容忍度將有助於主動元件在量產時的封裝可行性。此外相較於傳統利用乾蝕刻技術製作的脊狀波導，本架構的光波導具有成本與量產可行性的優勢。 在第二個部分，為了提升三維光路的靈活性，我們提出應用於垂直分光波導的三維分光器，以及應用於主動式光學網路的垂直轉換結構。在三維垂直分光器部分，其原理是利用主波導與分光波導的幾何寬度差異，並且在其中插入單石積體化且具有45˚微反射面的垂直分光器。此結構可同時完成垂直分光，以及電子層與光學元件層的光學訊號連接。在此研究中，我們實現一個具有不同分光比例的三維1×2垂直分光波導。當主波導的波導寬度從40 μm變換至70 μm，垂直分光效率可從20%:80%轉換至46%:54%，總體的光學傳輸效率約為-6 dB。在此結構中，光波導具有較寬鬆的元件封裝位移容忍度(約大於±13 µm at -1 dB)，適合應用於被動式的光學網路架構。 針對應用於主動式光學網路的垂直轉換結構，我們將其製作於三維光波導的表面。此垂直轉換結構不僅可以實現光路的垂直轉換，並且可以提供一個光學平台，將可電控式多重量子井(MQWs)整合於此垂直轉換結構上。在本研究中，我們實現一個1×3垂直轉換光路，並且利用紅外光攝影機觀察光波導輸出端的光點。其總光學耦合效率約為-5.33 dB，各個通道出口的耦合效率約為-10.81、-11.74、以及-8.45 dB。長直光波導的傳播損耗約為0.178 dB/cm。相較於長直光波導，本架構的1×3垂直轉換光路的總分光損耗約為1.57 dB。 最後，我們在SOI基板上實現一個具有雷射、光偵測器、驅動電路、以及放大電路的晶片等級光學連接模組。在本模組中，我們利用獨特的三維光路設計，連接模組發射端與接收端，面射型雷射與光偵測器則利用覆晶封裝技術將其整合至SOI基板的電子元件層上，形成完整的光學連接模組。從量測結果得知，雷射至光偵測器的光學耦合效率約為-2.19 dB，雷射的最大輸出光功率與最低臨界電流分別為3.27 mW以及1 mA。在高速訊號的測試中，當最低的雷射驅動電流為9mA時，我們成功驗證一個10-Gbps的無錯誤訊號傳輸(Error-Free)。經由實驗量測證實，本論文所提出的三維光學網路可用以實現一個高速傳輸且低功耗的晶片等級光學連接模組。
摘要(英)	In this dissertation, the researches focus on the development of SOB-based 3-D network optical path for chip-level optical interconnects. The researches can be divided into three major topics, including the point-to-point 3-D optical path, the flexible 3-D network optical path with vertical power splitter and vertical transition structure, and the implementation of SOI-based chip-level optical interconnects with lasers and PDs. Using 3-D network optical path, the electronic and optical circuits can be respectively built on the rear (electronics layer) and front (optics layer) side of SOI substrate using compatible fabrication process. Because of the unique separated photonics-electronics design, active photonics devices and passive optics can be easily integrated with electronics circuits in a single silicon chip, and the high-speed data transmission with low power consumption for chip-level optical interconnects can be also achieved. With respect to the research on the point-to-point 3-D optical path, the high-quality 45˚ micro-reflectors and crystalline silicon trapezoidal waveguides is realized on the SOI substrate using anisotropic wet-etching process. Using the 3-D optical path, there are three kinds of capability can be achieved, including the integration of high efficient laser and PD chips, the low-loss crystalline silicon waveguides, and the separated photonics-electronics design. From the measurement result, the transmission efficiency from input SMF to output MMF is -2.91 dB, and the propagation loss of silicon straight trapezoidal waveguides is as low as 0.404 dB/cm. A wide alignment tolerance of SMF-to-waveguide (> ±5 μm) and waveguide-to-MMF (> ±14 μm) is also achieved to facilitate the active device assembly. As compared to the conventional ridge waveguide using the dry-etching approach, the proposed 3-D optical path would be a cost-effective structure for the mass production. In the second part of this dissertation, we proposed the 3-D power splitter for vertically-splitting waveguide and the vertical transition structure for active network optical path. Respect to the vertically-splitting waveguide, it is designed by the concept of using waveguide width difference between bus waveguide and branch waveguide. The monolithically embedded vertically-splitting structure with sidewall angle of 45˚ is used to vertically split the light and simultaneously connect the optics layer with the electronics layer of SOI substrate in the proposed chip-level optical interconnect systems. In this research, we experimentally demonstrated the 3-D 1×2 vertically-splitting waveguide with various power splitting ratios. The total transmission efficiency of proposed waveguide is around -6 dB, and the power splitting ratio of optical path 1 to optical path 2 can be controlled from 20%:80% to 46%:54% as the upper width of bus waveguide adjusts from 40 to 70 μm. The proposed vertically-splitting waveguide also provides the wider alignment tolerance (larger than ±13 µm at -1 dB power variation) for the active photonics device assembly. The vertical-transition structures with 45˚ sidewall angle are first demonstrated in the SOI-based 3-D optical path. Such unique vertical-transition structures not only perform the vertical transition optical path but also provide a stage to integrate with the electrically controlled electro-absorption MQWs that is used to actively switch the optical path. Here, we experimentally demonstrated the 1×3 vertical-transition optical waveguide. Three clear light spots emitting from each output ports are observed by an IR camera. The total optical transmission efficiency can reach to -5.33 dB, and the corresponding optical transmission efficiency at output port 1, 2, and 3 are -10.81, -11.74, and -8.45 dB, respectively. A lower propagation loss of 0.178 dB/cm is also demonstrated by the cut-back method. Compared to the straight waveguide without any vertical-transition structures, the total splitter loss of 1×3 vertical-transition straight waveguide is 1.57 dB. Finally, we first demonstrated the chip-level optical interconnect module combined with a VCSEL chip, a PD chip, a driver IC, and an amplifier IC on a SOI substrate. The unique point-to-point 3-D optical path is used to connect optical signal between transmitter and receiver. In this research, the VCSEL and PIN PD chips are flip-chip integrated on the electrical layer of SOI substrate to achieve complete chip-level optical interconnects. A higher VCSEL-to-PD optical coupling efficiency of -2.19 dB, a maximum optical power of 3.27 mW, and a low threshold current of 1 mA are achieved. The error-free data transmission of 10-Gbps can be also demonstrated when VCSEL is operated at the driving current of 9 mA. These measurement results verify that the proposed chip-level optical interconnect could be operated at a higher data rate and a lower power consumption using the proposed SOI-based 3-D optical paths.
關鍵字(中)	★ 晶片等級光學連接模組 ★ 光學網路光路 ★ 導波式矽基光學平台 ★ 光波導	關鍵字(英)	★ Chip-Level Optical Interconnect ★ Network Optical Path ★ GW-SiOB ★ Waveguide
論文目次	Abstracts ............................................................................................................. I Abstracts in Chinese ..................................................................................................IV Acknowledgements ......................................................................................................VI Contents ............................................................................................................ VII Figure List ...........................................................................................................IX Table List ........................................................................................................... XV Chapter 1. Introduction ............................................................................................... 1 1.1 Demands of Optical Interconnects in Chip-Level Applications ....................................................... 3 1.2 Existing Technologies for Chip-Level Optical Interconnects ........................................................ 9 1.3 Research Objectives in This Dissertation ......................................................................... 14 Chapter 2. SOI-Based 3-D Optical Path for Chip-Level Optical Interconnects ........................................... 18 2.1. Introduction .................................................................................................... 18 2.2. Optical Design of 3-D Optical Path on SOI Substrate ............................................................. 21 2.3. Fabrication and Measurement Result of SOI-Based 3-D Optical Path ................................................ 26 2.4. Summary ......................................................................................................... 31 Chapter 3. SOI-Based 3-D 1×2 Vertically-Splitting Waveguide for Passive Network Optical Path ......................... 32 3.1. Introduction .................................................................................................... 32 3.2. Design of 3-D 1×2 Vertically-Splitting Waveguide on SOI Substrate ............................................... 34 3.3. Fabrication and Evaluation of 1×2 Vertically-Splitting Waveguide on SOI Substrate ............................... 41 3.4. Summary ......................................................................................................... 47 Chapter 4. SOI-Based Optical Waveguide with Multiple Vertical-Transition Output Ports for Active 3-D Network Optical Path ................................................................................................................. 48 4.1. Introduction .................................................................................................... 48 4.2. Design of 1×3 Vertical-Transition Optical Waveguide ............................................................. 52 4.3. Fabrication and Experimental Result of 1×3 Vertical-Transition Optical Waveguide ................................ 57 4.4. Summary ......................................................................................................... 62 Chapter 5. Implementation of SOI-Based Chip-Level Optical Interconnects with Lasers and PDs Using 3-D Optical Path ... 63 5.1. Introduction .................................................................................................... 63 5.2. Design of Proposed Chip-Level Optical Interconnects with Lasers and PDs ......................................... 66 5.3. Realization of Proposed Chip-Level Optical Interconnects with VCSEL and PD ...................................... 69 5.4. Characterization of Proposed Chip-Level Optical Interconnects with VCSEL and PD ................................. 72 5.5. Summary ......................................................................................................... 79 Chapter 6. Conclusions and Future Works .............................................................................. 80 References ........................................................................................................... 86 Publication Lists .................................................................................................... 94
參考文獻	[1]. M. B. Giles and I. Reguly, “Trends in high-performance computing for engineering calculations,” Phil. Trans. R. Soc. A, vol. 372, no. 2022, pp. 20130319, 2014 [2]. Sutter, Herb. "The free lunch is over: A fundamental turn toward concurrency in software." Dr. Dobb’s journal, vol. 30, no. 3, pp. 202-210, 2005 [3]. S. Vangal, Howard, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, . Finan, P. Iyer, A. Singh, T. Jacob, S. Jain, S. Venkataraman, Y. Hoskote, N. Borkar, “An 80-tile 1.28 TFLOPS network-on-chip in 65nm CMOS,” In IEEE International Solid-State Circuits Conference, San Fransisco, USA, 2007 [4]. M. B. Taylor, W. Lee, J. Miller, D. Wentzlaff, I. Bratt, B. Greenwald, H. Hoffmann, P. Johnson, J. Kim, J. Psota, A. Saraf, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, and A. Agarwal, “Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams,”. ACM SIGARCH Computer Architecture News, vol. 32, no. 2, pp. 2, 2004 [5]. D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” IEEE Computer Society, vol. 36, no. 3, pp. 153-164, 2008. [6]. J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys. A, vol. 95, no. 4, pp. 989–997, 2009. [7]. C. Batten, A. Joshi, V. Stojanov´c, and K. Asanovi´c, “Designing chip-level nanophotonic interconnection networks,” in Integrated Optical Interconnect Architectures for Embedded Systems. Springer New York, 2013 [8]. R. Kumar, V. Zyuban, and D. M. Tullsen. “Interconnections in multi-core architectures: Understanding mechanisms, Overheads and Scaling,” ISCA′05. Proceedings. 32nd International Symposium on. IEEE, 2005 [9]. D.Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE, vol. 97, no. 7, pp. 1166–1185, 2009 [10]. J. Howard, S. Dighe, S. R. Vangal, G. Ruhl, N. Borkar, S. Jain, V. Erraguntla, M. Konow, M. Riepen, M. Gries, G. Droege, T. Lund-Larsen, S. Steibl, S. Borkar, V. K. De, and R. V. D. Wijngaart, “A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling,” IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 173–183, 2011. [11]. S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W teraFLOPS processor in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 29-41, 2008 [12]. J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, and C. R. Das, “A low latency router supporting adaptivity for on-chip interconnects,” In Proceedings of the 42nd annual Design Automation Conference, CA, USA, 2005 [13]. M. Haney, R. Nair, and T. Gu, “Chip-scale integrated optical interconnects –A key enabler for future high performance computing,” In SPIE OPTO International Society for Optics and Photonics, 2012 [14]. R. Ho, P. Amberg, E. Chang, P. Koka, J. Lexau, G. Li, F. Y. Liu, H. Schwetman, I. Shubin, H. D. Thacker, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy , ”Silicon photonic interconnects for large-scale computer systems,” IEEE Micro, vol. 33, no. 1, pp. 68-78, 2013 [15]. Y. Arakawa, T. Nakamura, Y. Urino and T. Fujita, “Silicon photonics for next generation system integration platform,” Communications Magazine, IEEE, vol. 51, no. 3, pp. 72-77, 2013 [16]. D. A. B. Miller, “Physical reasons for optical interconnection,” Int. J. Optoelectron., vol. 11, no. 3, pp. 155–168, 1997. [17]. M. Haurylau et al., “On-chip optical interconnect roadmap: Challenges and critical directions,” IEEE J. Sel. Topics Quantum Electron., vol. 12, no. 6, pp. 1699–1705, 2007 [18]. R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. Stanley Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE, vol. 96, no. 2, pp. 230–247, 2008 [19]. M. Stucchi, S. Cosemans, J. V. Campenhout, Z. Tokei, and G. Beyer, “On-chip optical interconnects versus electrical interconnects for high-performance applications,” Microelectronic Engineering, vol. 112, pp. 84-91, 2013 [20]. S. Manipatruni, M. Lipson, and I. A. Young, “Device scaling considerations for nanophotonic CMOS global interconnects,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 19, no. 2, pp. 400-408, 2013 [21]. N. Bressona, S. Cristoloveanub, C. Mazuréa, F. Letertrea, and H. Iwaic, “Integration of buried insulators with high thermal conductivity in SOI MOSFETs: thermal properties and short channel effects,” Solid-State Electron, vol. 49, no. 9, pp. 1522–1528, 2005 [22]. T. Ernst, C. Tinella, C. Raynaud, S. Cristoloveanu, “Fringing fields in sub-0.1 mm fully depleted SOI MOSFETs: optimization of the device architecture,” Solid-State Electron. vol. 46, pp. 373-378, 2002 [23]. T. Ernst, and S. Cristoloveanu, “Buried oxide fringing capacitance: a new physical model and its implication on SOI device scaling and architecture,” in Proceedings of IEEE International SOI Conference, New York, 1999 [24]. B. Ciftcioglu, R. Berman, S. Wang, J. Hu, I. Savidis, M. Jain, D. Moore, M. Huang, E. G. Friedman, G. Wicks, and H. Wu, “3-D integrated heterogeneous intra-chip free-space optical interconnect,” Optics Express, vol. 20, no. 4, pp. 4331- 4331, 2012 [25]. A. Biberman and K. Bergman, “Optical interconnection networks for high-performance computing systems,” Reports on Progress in Physics, vol. 75, no. 4, pp. 046402, 2012 [26]. Y. Urino, Y. Noguchi, M. Noguchi, M. Imai, M. Yamagishi, S. Saitou, N. Hirayama, M. Takahashi, H. Takahashi, E. Saito, M. Okano, T. Shimizu, N. Hatori, M. Ishizaka, T. Yamamoto, T. Baba, T. Akagawa, S. Akiyama, T. Usuki, D. Okamoto, M. Miura, J. Fujikata, D. Shimura, H. Okayama, H. Yaegashi, T. Tsuchizawa, K. Yamada, M. Mori, T. Horikawa, T. Nakamura, and Y. Arakawa, “Demonstration of 12.5-Gbps optical interconnects integrated with lasers, optical splitters, optical modulators and photodetectors on a single silicon substrate,” Optics Express, vol. 20, no. 26, pp. B256-B263, 2012 [27]. H. Rong, R. Jones, A. Liu, O. Cohen, D. Hak, A. Fang, and M. Paniccia, “A continuous-wave Ramansilicon laser,” Nature, vol. 433, no. 7027, pp. 725-728, 2005 [28]. O. Boyraz and B. Jalali, “Demonstration of a silicon Raman laser,” Optics Express, vol. 12, no. 21, pp. 5269-5273, 2004 [29]. H. Rong, S. Xu, Y. H. Kuo, V. Sih, O. Cohen, O. Raday, and M. Paniccia, “Low-threshold continuous-wave Raman silicon laser,” Nature Photonics, vol. 1, no. 4, pp. 232-237, 2007 [30]. P. Markov, J. G. Valentine, and S. M. Weiss, “Fiber-to-chip coupler designed using an optical transformation,” Optics Express, vol. 20, no. 13, pp. 14705-14713, 2012 [31]. J. Inoue, T. Ogura, K. Kintaka, K. Nishio, Y. Awatsuji, and S. Ura, “Fabrication of embedded 45-degree micromirror using liquid-immersion exposure for single-mode optical waveguides,” Journal of Lightwave Technology, vol. 30, no. 11, pp. 1563-1568, 2012 [32]. L. H. Gabrielli and M. Lipson, “Integrated luneburg lens via ultra-strong index gradient on silicon,” Optics Express vol. 19, no. 21, pp. 20122-20127, 2011 [33]. J. F. Bauters, M. J. R. Heck, D. D. John, J. S. Barton, C. M. Bruinink, A. Leinse, R. G. Heideman, D. J. Blumenthal, and J. E. Bowers, “Planar waveguides with less than 0.1 dB/m propagation loss fabricated with wafer bonding.” Optics Express, vol. 19, no. 24, pp. 24090- 24101, 2011 [34]. W. Bogaerts, and S. K. Selvaraja, “Compact single-mode silicon hybrid rib/strip waveguide with adiabatic bends,” IEEE Photonics Journal, vol. 3, no. 3, pp. 422–432, 2011 [35]. R. F. Oulton, V. J. Sorger, D. A. Genov, D. F. P. Pile, and X. Zhang, “A hybrid plasmonic waveguide for subwavelength confinement and long-range propagation,” Nature Photonics, vol. 2, pp. 496-500, 2008 [36]. X. Li, H. Xu, X. Xiao, Z. Li, J. Yu, and Y. Yu, “Compact and low-loss silicon power splitter based on inverse tapers,” Optics Letters, vol. 38, no. 20, pp. 4220-4223, 2013 [37]. X. Guan, H. Wu, Y. Shi, and D. Dai, “Extremely small polarization beam splitter based on a multimode interference coupler with a silicon hybrid plasmonic waveguide,” Optics Letters, vol. 39, no. 20, pp. 259-262, 2014 [38]. A. Hosseini, S. Rahimi, X. Xu, D. Kwong, J. Covey, and R. T. Chen, “Ultracompact and fabrication-tolerant integrated polarization splitter,” Optics Letters, vol. 36, no. 20, pp. 4047-4049, 2011 [39]. G. Kim, J. W. Park, I. G. Kim, S. Kim, K. S. Jang, S. A. Kim, J. H. Oh, J. Joo, and S. Kim, “Compact-sized high-modulation-efficiency silicon Mach–Zehnder modulator based on a vertically dipped depletion junction phase shifter for chip-level integration,” Optics Letters, vol. 39, no. 8, pp. 2310-2313, 2014 [40]. A. Brimont, A. M. Gutierrez, M. Aamer, D. J. Thomson, F. Y. Gardes, J. M. Fedeli, G. T. Reed, J. Martí, P. Sanchis, “Slow-light-enhanced silicon optical modulators under low-drive-voltage Operation,” IEEE Photonics Journal, vol. 4, no. 5, pp. 1306-1315, 2012 [41]. W. M. J. Green, M. J. Rooks, L. Sekaric, and Y. A. Vlasov, “Ultra-compact, low RF power, 10 Gb/s silicon Mach-Zehnder modulator,” Optics Express, vol. 15, no. 25, pp. 17106-17113, 2007 [42]. S. Assefa, F. Xia, S. W. Bedell, Y. Zhang, T. Topuria, P. M. Rice, and Y. A. Vlasov, “CMOSintegrated 40GHz germanium waveguide photodetector for on-chip optical interconnects,” In Optical Fiber Communication Conference (OFC), OSA. 2009 [43]. O. Fidaner, A. K. Okyay, J. E. Roth, R. K. Schaevitz, Y. H. Kuo, K. C. Saraswat, J. S. Harris, Jr., and D. A. B. Miller, “Ge–SiGe quantum-well waveguide photodetectors on silicon for the near-infrared,” IEEE Photonics Technology Letters, vol. 19, no. 20, pp. 1631-1633, 2007 [44]. L. Chen, and M. Lipson. "Ultra-low capacitance and high speed germanium photodetectors on silicon." Optics Express, vol.17, no.10, pp. 7901-7906, 2009 [45]. A. W. Fang, M. N. Sysak, B. R. Koch, R. Jones, E. Lively, Y. H. Kuo, D. Liang, O. Raday, and J. E. Bowers, “Single-wavelength silicon evanescent lasers,” IEEE J. Sel. Topics Quantum Electron. vol. 15, no.3, pp. 535–544, 2009 [46]. T. Shimizu, N. Hatori, M. Okano, M. Ishizaka,Y. Urino, T. Yamamoto, M. Mori, T. Nakamura, and Y. Arakawa, “High density hybrid integrated light source with a laser diode array on a silicon optical waveguide platform for inter-chip optical interconnection,” In 8th IEEE Int. Conf. on Group IV Photonics, London, 2011 [47]. K. Narayanan, A. W. Elshaari and S. F. Preble, “Broadband all-optical modulation in hydrogenated-amorphous silicon waveguides,” Optics Express, vol. 18, no. 10, pp. 9809-9814, 2010 [48]. S. J. Chang, C. Y. Ni, Z. Wang, and Y. J. Chen, “A compact and low power consumption optical switch based on microrings,” IEEE Photon. Technol. Lett., vol. 20, no.12 pp. 1021–1023, 2008 [49]. C. Husko, A. D. Rossi, S. Combrié, Q. V. Tran, F. Raineri, and C. W. Wong, “Ultrafast all-optical modulation in GaAs photonic crystal cavities,” Appl. Phys. Lett. Vol. 94, no. 2, pp. 021111, 2009 [50]. A. W. Fang, B. R. Koch, R. Jones, E. Lively, D. Liang, Y. H. Kuo, and J. E. Bowers, “A distributed bragg reflector silicon evanescent laser,” IEEE Photon. Technol. Lett, vol. 20, no. 20, pp. 1667-1669, 2008 [51]. Y. Halioua, A. Bazin, P. Monnier, T. J. Karle, G. Roelkens, I. Sagnes, R. Raj, and F. Raineri, “Hybrid III-V semiconductor/silicon nanolaser,” Optics Express, vol. 19, no. 10, pp. 9221-9231, 2011 [52]. D. Vermeulen, S. Selvaraja, P. Verheyen, G. Lepage, W. Bogaerts, P. Absil, D. V. Thourhout, and G. Roelkens, “High-efficiency fiber-to-chip grating couplers realized using an advanced CMOS-compatible Silicon-On-Insulator platform,” Optics Express, vol. 18, no. 17, pp. 18278-18283, 2010 [53]. A. Mekis, S. Gloeckner, G. Masini, A. Narasimha, T. Pinguet, S. Sahni, and D. Dobbelaere, “A grating-coupler-enabled CMOS photonics platform,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 17, no. 3, pp. 597-608, 2011 [54]. L. Liu, M. Pu, K. Yvind and J. M. Hvam, “High-efficiency, large-bandwidth silicon-on-insulator grating coupler based on a fully-etched photonic crystal structure,” Applied physics letters, vol. 96, no. 5, pp. 051126, 2010 [55]. T. Gu, R. Nair, and M. W. Haney, “Chip-level multiple quantum well modulator-based optical interconnects,” Journal of Lightwave Technology, vol. 31, no. 24, pp. 4166-4174, 2013 [56]. P. Koonath and B. Jalali, “Multilayer 3-D photonics in silicon,” Optics Express, vol.15, no. 20, pp. 12686-12691, 2007 [57]. S. Zhu, Q. Fang, M. B. Yu, G. Q. Lo, and D. L. Kwong, “Propagation losses in undoped and n-doped polycrystalline silicon wire waveguides,” Optics Express, vol. 17, no. 23, pp. 20891-20899, 2009 [58]. T. M. B. Masaud, A. Tarazona, E. Jaberansary, X. Chen, G. T. Reed, G. Z. Mashanovich, and H. M. H. Chong, “Hot-wire polysilicon waveguides with low deposition temperature,” Optics Letters, vol. 38, no. 20, pp. 4030-4032, 2013 [59]. J. Kang, Y. Atsumi, M. Oda, T. Amemiya, N. Nishiyama, and S. Arai, “Low-loss amorphous silicon multilayer waveguides vertically stacked on silicon-on-insulator substrate,” Jpn. J. Appl. Phys., vol. 50, no. 12, pp. 120208, 2011 [60]. S. Zhu, G. Q. Lo, and D. L. Kwong, “Low-loss amorphous silicon wire waveguide for integrated photonics: effect of fabrication process and the thermal stability,” Optics Express, vol. 18, no. 24, pp. 25283-25291, 2010 [61]. H. C. Lan, H. L. Hsiao, C. C. Chang, C. H. Hsu, C. M. Wang, and M. L. Wu, “Monolithic integration of elliptic-symmetry diffractive optical element on silicon-based 45° micro-reflector,” Optics Express, vol. 17, no. 23, pp. 20938-20944, 2009 [62]. S. H. Tao, Q. Fang, J. F. Song, M. B. Yu, G. Q. Lo, and D. L. Kwong, “Cascade wide-angle Y-junction 1 × 16 optical power splitter based on silicon wire waveguides on silicon-on-insulator” Optics express, vol. 16, no. 26, pp. 21456-21461, 2008 [63]. Y. Zhang, S. Yang, A. E. Lim, G. Q. Lo, C. Galland, T. B. Jones, and M. Hochberg, “A compact and low loss Y-junction for submicron silicon waveguide,” Optics Express, vol. 21, no. 1, pp. 1310-1316, 2013 [64]. Z. Sheng, Z. Wang, C. Qiu, L. Li, A. Pang, A. Wu, X. Wang, S. Zou, F. Gan, “A Compact and Low-Loss MMI Coupler Fabricated With CMOS Technology,” IEEE Photonics Journal, vol. 4, no. 6, pp. 2272-2277, 2012 [65]. A. O. Monux, L. Z. Peche, A. M. Novo, I. M. Fernandez, R. Halir, J. G. W. Perez, P. Cheben, and J. H. Schmid, “High-performance multimode interference coupler in silicon waveguides with subwavelength structures,” IEEE Photonics Technology Letters, vol. 23, no. 19, pp. 1406-1408, 2011 [66]. I. Park, H. S. Lee, H. J. Kim, K. M. Moon, S. G. Lee, B. H. O, S. G. Park, and E. H. Lee, “Photonic crystal power-splitter based on directional coupling,” Optics Express, vol. 12, no. 15, pp. 3599-3604, 2004 [67]. A. Ghaffari, F. Monifi, M. Djavid, and M. S. Abrishamian, “Analysis of photonic crystal power splitters with different configurations,” Journal of Applied Sciences, vol. 8, no. 8, pp. 1416-1425, 2008 [68]. J. Xing, K. Xiong, H. Xu, Z. Li, X. Xiao, J. Yu, and Y. Yu, “Silicon-on-insulator-based adiabatic splitter with simultaneous tapering of velocity and coupling,” Optics Letters, vol. 38, no. 13, pp. 2221-2223, 2013 [69]. A. Ghaffari, F. Monifi, M. Djavid, and M. S. Abrishamian, “Photonic crystal bends and power splitters based on ring resonators,” Optics Communications, vol. 281, no. 23, pp. 5929-5934, 2008 [70]. H. S. Chu, P. Bai, E. P. Li, and W. R. Hoefer, “Hybrid dielectric-loaded plasmonic waveguide-based power splitter and ring resonator: compact size and high optical performance for nanophotonic circuits” Plasmonics, vol. 6, no. 3, pp. 591-597, 2011 [71]. A.W. Poon, X. Luo, F. Xu ; H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proceedings of the IEEE, vol. 97, no. 7, pp. 1216-1238, 2009 [72]. N. S. Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4x4 hitless silicon router for optical Networks-on-Chip (NoC),” Optics Express, vol. 16, no. 20, pp. 15915-15922, 2008 [73]. R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Five-port optical router for photonic networks-on-chip,” Optics Express, vol. 19, no. 21, pp. 20258-20268, 2011 [74]. T. Hu, H. Shao, L. Yang, C. Xu, M. Yang, H. Yu, X. Jiang, J. Yang, “Four-port silicon multi-wavelength optical router for photonic networks-on-chip,” IEEE Photonics Technology Letters, vol. 25, no. 23, pp. 2281-2284, 2013 [75]. Y. P. Varshni, “Temperature dependence of the energy gap in semiconductors,” Physica, vol. 34, no. 1, pp. 49–154, 1967 [76]. H.Ohe, H. Shimizu, Y. Nakano, “InGaAlAs multiple-quantum-well optical phase modulators based on carrier depletion,” IEEE Photonics Technology Letters, vol. 19, no. 22, pp. 1816-1818, 2007 [77]. P. G. Goetz, R. Mahon , T. H. Stievater, W. S. Rabinovich, and S. C. Binari, “High-speed large-area surface-normal multiple quantum well modulators” In Optical Science and Technology, SPIE′s 48th Annual Meeting, 2004 [78]. J. Pereiro, C. Rivera, Á . Navarro, E. Muoz, R. Czernecki, S. Grzanka, and M. Leszczynski, “Optimization of InGaN–GaN MQW photodetector structures for high-responsivity performance,” IEEE Journal of Quantum Electronics, vol. 45, no. 6, pp. 617-622, 2009 [79]. P. Chaisakul, D. Marris-Morini, G. Isella, D. Chrastina, X. L. Roux, S. Edmond, E. Cassan, J. R. Coudevylle and L. Vivien, “Ge/SiGe multiple quantum well photodiode with 30 GHz bandwidth,” Applied Physics Letters, vol. 98, no. 13, pp. 131112-131112, 2011 [80]. M. S. Tobin and J. D. Bruno, "Quantum-confined Stark effect modulator based on multiple triple-quantum welts," J. Appl. Phys., vol. 89, no. 3 pp. 1885-1889, 2001 [81]. D. A. B. Miller, D. S. Chemla, and S. S. Rink, “Electroabsorption of highly confined systems: Theory of the quantum‐confined Franz–Keldysh effect in semiconductor quantum wires and dots,” Applied PhyLletters, vol. 52, no. 25, pp. 2154-2156, 1988 [82]. N. N. Feng, D. Feng, S. Liao, X. Wang, P. Dong, H. Liang, C. C. Kung, W. Qian, J. Fong, R. Shafiiha, Y. Luo, J. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “30GHz Ge electro-absorption modulator integrated with 3μm ilicon-on-insulator waveguide,” Optics Express, vol. 19, no. 8, pp. 7062-7067, 2011 [83]. S. Ren, Y. Rong, S.A. Claussen, R.K. Schaevitz, T.I. Kamins, J. S. Harris, D. A. B. Miller, “Ge/SiGe Quantum Well Waveguide Modulator Monolithically Integrated With SOI Waveguides Ge/SiGe,” IEEE Photonics Technology Letters, vol. 24, no. 6, pp. 461-463, 2012 [84]. J. Liu, M. Beals, A. Pomerene, S. Bernardis, R. Sun, J. Cheng, L. C. Kimerling and J. Michel, ”Waveguide-integrated, ultralow-energy GeSi electro-absorption modulators,” Nature Photonics, vol. 2, no. 7, pp. 433-437, 2008 [85]. P. Chaisakul, D. M. Morini, M. S. Rouifed, G. Isella, D. Chrastina, J. Frigerio, X. L. Roux, S. Edmond, J. R. Coudevylle, and L. Vivien, “23 GHz Ge/SiGe multiple quantum well electro-absorption modulator,” Optics Express, vol. 20, no. 3, pp. 3219-3224, 2012 [86]. T. Spuesens, J. Bauwelinck, P. Regreny, and D. V. Thourhout, “Realization of a compact optical interconnect on silicon by heterogeneous integration of III–V,” IEEE Photon. Technol. Lett., vol. 25, no. 14, pp. 1332-1335, 2013 [87]. W. Fang, H. Park, O. Cohen, R. Jones, M. J. Paniccia, and J. E. Bowers, ” Electrically pumped hybrid AlGaInAs-silicon evanescent laser,” Optics Express, vol. 14, no. 20, pp. 9203-9210, 2006 [88]. N. Fujioka, T. Chu, and M. Ishizaka, “Compact and low power consumption hybrid integrated wavelength tunable laser module using silicon waveguide resonators,” Journal of Lightwave Technology, vol. 28, no. 21, pp. 3115-3120, 2010 [89]. R Swanepoel, “Determination of surface roughness and optical constants of inhomogeneous amorphous silicon films,” J. Phys. E: Sci. Instrum., vol. 17, no. 10, pp. 896-903, 1984 [90]. D. Liang, M. Fiorentino, T. Okumura, H.-H. Chang, D. T. Spencer, Y.-H. Kuo, A. W. Fang, D. Dai, R. G. Beausoleil, and J. E. Bowers, “Electrically-pumped compact hybrid silicon microring lasers for optical interconnects,” Optics Express, vol. 17, no. 22, pp. 20355–20364, 2009 [91]. J. Lousteau, D. Furniss, A. B. Seddon, T. M. Benson, A. Vukovic, and P. Sewell, “The single-mode condition for silicon-on-insulator optical rib waveguides with large cross section,” Journal of Lightwave Technology, vol. 22, no. 8, pp. 1923-1929, 2004 [92]. R. A. Soref, J. Schmidtchen, and K. Petermann, Large single-mode rib waveguides in GeSi-Si and Si-on-SiO2,“IEEE Journal of Quantum Electronics, vol. 27, no. 8, pp. 1971-1974, 1991
指導教授	伍茂仁(Mount-learn Wu)	審核日期	2015-5-13
推文	facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu
網路書籤	Google bookmarks   del.icio.us   hemidemi   myshare