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姓名 朱冠銘(Kuan-ming Chu) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 可同步優化低壓降線性穩壓器與其誤差放大器的自動化設計方法
(Simultaneous Optimization Approach for Low Dropout Regulator and Its Error Amplifier)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 在系統單晶片(System on chip, SoC)的設計中,將不同功能的類比、數位或是射頻電路都整合在一顆晶片內,每個區塊電路所需要的電壓往往都不一樣,系統單晶片的供應電源往往是單一電壓,於是就需要電壓轉換器來將供應電源轉換成每塊電路需要的供應電壓。有著低功率、輸出漣波電壓很小、抗雜訊等優點的低壓降線性穩壓器就常常被應用在轉換電壓上。本論文提出一套低壓降線性穩壓器自動化設計的流程,依靠非線性規劃(Nonlinear programming)、gm/ID的設計概念以及電壓驅動的方法改善傳統幾何演算法的精準度以及效率。誤差放大器(Error amplifier)和低壓降線性穩壓器可以在自動化流程中同時做互相考慮以及最佳化的動作,使整體電路的成本減少。整個流程以Matlab和Hspice來實現,並整合成一個完整的程式。從實驗數據跟傳統的幾何演算法設計流程做個比較,本論文所提出的方法,可以提高公式精準度,同時更可以在相同的規格下,在短時間內找出優於傳統幾何演算法的電路設計。
摘要(英) In typical SoC (System on chip, SoC) designs, analog, digital and RF circuits are integrated in a single chip. Because the supply voltage of each circuit block may not the same, voltage converters are often required to generate the required supply voltage of each block from the outside power source. Due to its low power, small ripple and low noise properties, low-dropout linear regulators (LDO) are often used in SoC chips. This thesis proposes a design automation process for optimal sizing of low dropout linear regulator. Based on the nonlinear programming and gm/ID design concept, a bias-driven methodology is adopted to improve the accuracy and efficiency of the traditional approach based on geometric programming. The device in the low dropout linear regulator and its error amplifier are both considered in the optimization process for reducing the overall circuit cost. The proposed automation process has been implemented with Matlab and Hspice. As demonstrated in the experiments, the proposed approach can achieve the required specifications with the shortest computation time and the lowest hardware cost compared to previous approaches.
關鍵字(中) ★ 自動化設計
★ 低壓降線性穩壓器關鍵字(英) ★ LDO
★ low dropout regulator論文目次 摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 ix
第一章、 緒論 1
1-1 研究動機 1
1-2 相關研究 6
1-3 論文結構 10
第二章、 背景 11
2-1 低壓降線性穩壓器 11
2-1-1 電路架構 11
2-1-2 傳輸元件 12
2-1-3 壓降電壓 15
2-1-4 線性調節率 16
2-1-5 負載調節率 17
2-1-6 靜態電流 18
2-1-7 轉換效率 19
2-1-8 暫態響應 20
2-2 電壓驅動設計方法 24
2-2-1 gm/ID的特性 25
2-2-2 建立gm/ID和gds/ID表格 28
2-3 非線性規劃 29
2-4 設計尺寸 30
第三章、 自動化設計 32
3-1 自動化設計流程 32
3-2 穩態分析 34
3-3 設計偏壓點和變數 35
3-4 設定條件限制 37
3-4-1 穩定度條件限制 37
3-4-2 效能條件限制 44
3-4-3 飽和區條件限制 47
3-4-4 靜態功率消耗條件限制 48
3-5 目標函數 50
3-5-1 面積目標函數 50
3-5-2 功率消耗目標函數 51
3-5-3 穩定時間目標函數 52
第四章、 實驗結果與分析 55
4-1 實驗環境 55
4-2 實驗結果 55
4-2-1 最佳化穩定時間實驗結果 57
4-2-2 最佳化功率消耗和面積實驗結果 58
4-2-3 最佳化功率消耗、面積和穩定時間實驗結果 59
4-2-4 其他實驗結果比較 62
第五章、 結論 64
參考文獻 65
參考文獻 [1] On line source, Expreview, from http://www.expreview.com/8498.html
[2] Y.-H. Lee, K.-H. Chen, “A 65nm Sub-1V Multi-Stage Low-Dropout (LDO) Regulator Design for SoC Systems”, IEEE International Conference on Circuits and Systems, 2010.
[3] G. A. Rincon-Mora, “Current Efficient, Low Voltage, Low Dropout Regulators”, Ph.D. Dissertation, Elect. Comp. Eng. Dept., Georgia Inst of Technol., Atlanta, 1996.
[4] W. Gao, R. Hornsey, “A Power Optimization Method for CMOS Op-amps Using Sub-space Based Geometric Programming”, IEEE Design Automation and Test in Europe, 2010.
[5] S. DasGupta, P. Mandal, “An Automated Design Approach for CMOS LDO Regulators”, Asia and South Pacific Design Automation Conference, 2009.
[6] Y.-S. Shyu, “Low Operating Current Analog Integrated Circuits”, Ph.D Dissertation, National Chiao Tung University, Taiwan, 2002.
[7] B. S. Lee, “Technical Review of Low Dropout Voltage Regulator Operation and Performance”, Application Report, Aug. 1999.
[8] 詹立宇, "可改善幾何演算法之精準度的電壓趨動運算放大器自動化設計方法," 國立中央大學電機工程研究所碩士論文, July 2011
[9] H. Daoud Dammak, S. Bensalem, S. Zouari, and M. Loulou, “Design of Folded Cascode OTA in Different Regions of Operation through gm/ID Methodology”, World Academy of Science, Engineering and Technology 45 2008.
[10] M. S. Bazarar, H. D. Sherali, C. M. Shetty, “Nonlinear Programming”, Wiley, 1993, 2nd ed.
[11] C.-W. Lin, P.-D. Sue, Y.-T. Shyu, S.-J Chang, “A Bias-Driven Approach for Automated Design of Operational Amplifiers”, IEEE VLSI Design Automation and Test, 2009.
[12] Z.-M. Wu, Q.-Y. Fengl, Q.-Y. Xiang, “A Novel and Simple 0.18m CMOS Sub-1V Low-Dropout Regulator”, IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010.
[13] Z. Kamal, Q. Hassan, Z. Mouhcine, “Full On Chip Capacitance Pmos Low Dropout Voltage Regulator”, IEEE Conference on Multimedia Computing and Systems, 2011.
[14] S. S. Chong, P. K. Chan, “A Quiescent Power-Aware Low-Voltage Output Capacitorless Low Dropout Regulator for SoC Applications”, IEEE International Symposium on Circuits and Systems, 2011.
[15] V. Gupta, G. A. Rincon-Mora, P. Raha, “Analysis and Design of Monolithic, High PSR, Linear Regulators for SoC Applications”, IEEE International SOC Conference, 2004.
[16] 趙晏廷,「運算放大器之自動化設計流程及形為模型研究」,國立中央大學電機工程學系碩士論文,2007年7月。
[17] H.-Y. Luo, H.-W. Li, L.-C. Yeh, C.-N. Jimmy Liu, “Automated Synthesis Design Flow of Power Converter Circuits Aimed at SOC Applications”, IEEE International Symposium on Integrated Circuits, 2011.
[18] Gabriel A. Rincon-Mora, “Analog IC Design with Low-Dropout Regulators”, McGraw-Hill, 2009.
[19] B. Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw-Hill Higher Education, 2001.
指導教授 劉建男(Chien-Nan Jimmy Liu) 審核日期 2012-8-21 推文 plurk
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