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姓名 李肇軒(Tsao-Hsuan Lee) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 適用於3GPP-LTE/LTE-A系統下的高吞吐量新式交換網路之渦輪解碼器
(High-Throughput Turbo Decoder Design with New Interconnection Network for LTE/LTE-A System)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 在本論文中我們設計並實現了應用於LTE/LTE-A的高吞吐量渦輪碼設計。為了支援高傳輸量,使用了8套 radix-4 MAP平行SISO解碼器。而在解碼流程上,我們採用了滑動視窗解碼來提升解碼速度,另外預熱處理機制則用來補償多平行架構產生的解碼效能損耗。
接著我們運用了四種技巧來改善硬體設計。首先利用原地處理的概念將MAP解碼器內的α記憶體大小縮減一半,使得硬體總面積下降;再來藉著將前半次及後半次疊代運算疊合以縮減中間的解碼時間,使得解碼效率得到提升,進一步也提升了渦輪解碼器的吞吐量;第三項著重在交換網路的部分,我們更進一步地利用了QPP交錯器的特性,設計出一套擁有單純旋轉器及控制邏輯的新式交換網路,減少了交換網路的運算次數;最後一項改善是解決了多平行配上高基數演算的高吞吐量設計下,額外產生的特殊記憶體衝突。利用簡單的判斷條件配合額外的多工器交換存取或寫入的位址及資料。
在實作的部分利用 Design Compiler及 IC Compiler合成並選用TSMC 90nm CMOS製程,最後驗證我們的渦輪碼設計可以操作在406MHz下,並提供511Mbps的高吞吐量。摘要(英) In this paper, we design and implement a high-throughput turbo decoder for the 3rd Generation Partnership Project (3GPP) Long Term Evolution-Advanced (LTE-advanced) system. To support the high data rate, we adopts eight radix-4 parallel soft-in/soft-output MAP decoders. We adopt MAP decoding with sliding window mechanism to decrease decoding time. And we also use the warm-up scheme to compensate the performance loss. Besides, The properties of quadratic permutation polynomial (QPP) interleaver are exploited to reduce the complexity of the switch network between memory and MAP decoder.
Four techniques are used to improve the hardware design. First, the in-place algorithm is adopted to decrease the size of α-memory in MAP decoder , and hence the overall area can be reduced. Next, the processing periods of the last window in the first half iteration and the first window in the second half iterations are scheduled to be overlapped, Consequently, the decoding time is reduced and the throughput of the turbo decoder can be enhanced. The interconnection network is designed elaborately. A new interconnection network is proposed with a simple rotator and control logic. Using simple conditional judgement with extra multiplexers to exchange the address and memory data, we can support parallel processing of the turbo decoding. In addition, We achieve non-conflict memory access under high parallel and high radix hardware design for 188 modes .
From synthesis result, this work can operate at 406 MHz to offer decoding data rate up to 511 Mbps in 90nm CMOS technology.關鍵字(中) ★ 渦輪碼 關鍵字(英) 論文目次 目錄 .. v
圖示目錄 viii
表格目錄 .. x
第一章 緒論 1
1.1 簡介 ... 1
1.2 動機 ... 2
1.3 論文組織 ... 2
第二章 渦輪碼原理及規格 3
2.1 渦輪碼編碼 ... 3
2.1.1 渦輪碼編碼原理 3
2.1.2 渦輪碼編碼架構 4
2.2 渦輪碼解碼 ... 5
2.2.1 最大可能性對數比值 6
2.2.2 渦輪碼解碼架構 .. 11
2.2.3 渦輪碼效能分析 .. 12
2.3 LTE-A渦輪碼規格 13
2.3.1 LTE-A渦輪碼架構 . 13
2.3.2 LTE-A交錯器 . 13
第三章 解碼器設計 .. 16
3.1 最大對數事後機率演算法 . 16
3.2 預處理滑窗解碼流程時序 . 18
3.2.1 滑動視窗解碼 .. 18
3.2.2滑動視窗解碼比較 ... 21
3.3 高基數與多平行架構 . 21
3.3.1 高基數架構 .. 22
3.3.2 多平行架構 .. 25
3.4 提升硬體效率設計 . 29
3.4.1 節省狀態運算單元暫存記憶體 .. 29
3.4.2 增加硬體運算效率的解碼排程 .. 34
第四章 解碼硬體的改良 .. 39
4.1 交錯器 . 39
4.1.1 二次置換多項式交錯器特性 .. 40
4.1.2 旋轉器網路 .. 42
4.1.3 所提出之交換網路設計 .. 42
4.2 高吞吐量設計產生之記憶體衝突 . 44
4.2.1 多平行與高基數下記憶體配置 .. 44
4.2.2 記憶體衝突 .. 45
4.2.3 所提出之免衝突設計 .. 47
第五章 硬體實現 .. 49
5.1 主要運算單元 . 50
5.1.1 分支運算單元 .. 50
5.1.2 狀態運算單元 .. 51
5.1.3 補償挑選器 .. 53
5.1.4 補償單元 .. 55
5.1.5 LLR單元 56
5.2 選擇交換網路 . 57
5.2.1 位址產生單元 .. 57
5.2.2 交換網路單元 .. 59
5.2.3 節省硬體成本 .. 64
5.3 邊界交換網路 . 65
5.4 記憶體寫入/讀取位置交換(特殊區塊大小) . 70
5.5 整體硬體安排 . 75
5.6 系統效能模擬 . 76
5.7 硬體實現 . 77
5.8 合成結果 . 79
5.9 佈局結果 . 81
5.10 硬體實作比較 ... 84
第六章 結論 .. 86
參考文獻 87參考文獻 [1] C. Berrou, A. Glavieux and P. Thitimajshima, "Near Shannon limit error-correcting coding and decoding: Turbo Codes," in Proc. IEEE Int. Conf. Commun. ICC’93, Geneva, Switzerland, May 1993, pp. 1064-1070.
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[12] Ahmed, Ashfaq; Awais, Muhammad; Rehman, Ata Ur; Maurizio, Martina; Masera, “A
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[14] Jen-Yu Hou, “Design and Implementation of Turbo Decoder for 3GPP-LTE Advanced
Systems,” Master thesis, National Centural University, July, 2011.指導教授 蔡佩芸(Pei-Yun Tsai) 審核日期 2013-8-6 推文 plurk
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