博碩士論文 995201037 詳細資訊




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姓名 王昭穎(Chao-Ying Wang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 具有寬負載調節能力之高效率數位控制電流模式直流對直流降壓轉換器
(A High-Efficiency Digitally Controlled Current-Mode DC-DC Buck Converter with Wide-Load Regulation)
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摘要(中) 如何延長攜帶式電子產品的使用時間為一大重要議題,其中一種解決方式為增加電池之蓄電量,另一種方式為減少功率消耗、提高電源管理積體電路的功率轉換效率。切換式直流對直流穩壓器具有寬負載調節能力,適合應用於攜帶式電子產品之電力系統中,此外,數位控制之切換式穩壓器具有高度的設計彈性,系統參數可程式化修改,於不同製程下電路具有延伸性與重複使用的特質。
本論文所提出之數位控制電流模式降壓轉換器,其系統設計是建立於數學推導,並輔以行為模型加以驗證其正確性。基於功率級不足的相位邊限,系統中需要數位補償器來改善系統穩定度,數位之比例-積分-微分控制器即是用來增加功率級的相位邊限並擴大系統頻寬。比例-積分-微分控制器先於連續時域下設計,再利用雙線性轉換式得出離散時域之控制器,轉換後的相位與系統頻寬並無發生失真之現象。於控制迴路中,類比數位轉換器與數位脈衝寬度調變器的解析度需依據系統的需求來設計,以避免降壓轉換器的輸出發生極限循環振盪。可預測電流控制法則應用於此電流模式降壓轉換器中,結合電感電流與誤差電壓兩項資訊,有效調整控制訊號的工作週期,使降壓轉換器能調節出所需的直流電壓準位。
降壓轉換器中之延遲線類比數位轉換器,其概念是建立於時間-數位之轉換,此類比數位轉換器具有四位元解析度,最低有效位元為10毫伏特。比例-積分-微分控制器以查表法實現,可有效降低面積消耗。計數器-比較器架構之數位脈衝寬度調變器具有精確的工作週期調變能力,其解析度為8位元,時間解析度為3.9奈秒。數位電流感測器採用連續近似演算法,將電流感測與量化整合為一,具有4位元解析度,最低有效位元為93.2毫安培,電流感測範圍0-1.4安培。適應性停滯時間控制器具有快速的切換節點電壓偵測能力,可改善功率轉換效率並避免短路電流的發生。所提出的緩啟動電路可避免降壓轉換器於啟動時引起突發之大電流,進而保護元件免於損毀,此緩啟動電路可完整地整合至晶片中,無需外接元件。
本數位控制電流模式降壓轉換器是以0.18μm CMOS製程實現而成,晶片面積為2.66平方毫米。此降壓轉換器之輸入電壓範圍為2.3至4.4伏特,輸出電壓準位為1.8伏特,切換頻率為1百萬赫茲,負載電流範圍0-1安培。於500毫安培負載電流暫態下,產生之過衝或下衝電壓為230毫伏特,恢復時間為23微秒。線性調節度為9.5μV/mV,負載調節度為18μV/mA。最大功率轉換效率可達到92%。
摘要(英) For portable electronics, the extension of usage time is an essential consideration. One solution is to increase the capacity of batteries. Another solution is to reduce the power consumption, that is to say, increase the power conversion efficiency of power management IC. For the requirement of wide-load regulation, the DC-DC switching regulator is suitable to employ in portable power system. Besides, the digitally-controlled DC-DC converter offers high-degree flexibility, programmable system para- meters, scalable and reusable hardware with difference processes.
System design of the digital current-mode Buck converter is based on the mathematical derivations, and verified by using behavioral models. Due to insufficient phase margin of converter power stage, a digital compensator is necessary. The digital PID controller is used to increase the phase margin of converter power stage and extend the system bandwidth. PID controller is first devised in continuous -time domain, and then converted to discrete-time domain by the bilinear transform with frequency prewarping. Phase and system bandwidth is well-mapping after transformation. There are two quant- izers ADC and DPWM in control loop, the resolutions of this two circuits are dependent on system requirements and no-limit-cycle oscillation conditions to prevent the undesirable oscillation in output voltage. Predictive current control law is employed in digital current-mode controller. Based on the information of inductor current and voltage error between feedback voltage and reference voltage, the duty cycle of PWM is accordingly adjusted to control the converter to regulate the output voltage to the desired dc level.
ADC used in digital controller is based on delay-line architecture with time-to-digital conversion, the resolution is 4 bits with 10mV LSB. PID controller is realized with look-up tables to reduce area cost. DPWM uses the counter-comparator architecture to provide accurate modulation of PWM duty cycle, the resolution is 8 bits with 3.9ns time resolution. Digital current sensor based on successive-approx- imation algorithm can realize the current sensing and quantization into single procedure, resolution is 4 bits with 93.2mA LSB, sensing range is 0-1.4A. Adaptive dead-time controller with fast detection of switching node voltage is utilized to improve power conversion efficiency and prevent occurrence of shoot-through current. A monolithic on-chip soft-start circuit is used to avoid abrupt inrush current during start-up period.
The proposed digitally-controlled current-mode Buck converter is implemented by 0.18-μm CMOS process with 2.66mm2 chip area. Input voltage ranges from 2.3V to 4.4V, the output voltage is 1.8V, switching frequency is 1MHz, and a wide load current range 0-1A. A 230mV voltage overshoot/und- ershoot is achieved with 26μs recovery time during 500mA load current transient. The line regulation is 9.5μV/mV, and the load regulation is 18μV/mA. The maximum power efficiency is achieved with 92%.
關鍵字(中) ★ 直流對直流穩壓器
★ 比例-積分-微分控制器
★ 雙線性轉換
★ 類比數位轉換器
★ 數位脈衝寬度調變器
★ 極限循環振盪
★ 可預測電流控制
★ 數位電流感測器
關鍵字(英) ★ DC-DC Converter
★ PID Controller
★ Bilinear Transform
★ Analog-to-Digital Converter (ADC)
★ Digital Pulse-Width Modulator (DPWM)
★ Limit-Cycle Oscillation
★ Predictive Current Control
★ Digital Current Sensor
論文目次 大綱 i
Abstract ii
Acknowledgements iii
Contents iv
List of Figures vii
List of Tables xi
1 Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Thesis Organization 2
2 Fundamentals of DC-DC Buck Converter 4
2.1 Analysis of Steady-State Buck Converter 4
2.1.1 Inductor Volt-Second Balance 5
2.1.2 Capacitor Charge Balance 7
2.1.3 Inductor Current Ripple Estimation 8
2.1.4 Output Voltage Ripple Estimation 8
2.2 Steady-State Buck Converter Modeling 9
2.2.1 Equivalent Circuit Model 9
2.2.2 Power Conversion Efficiency 12
2.3 Dynamic Buck Converter Modeling 13
2.3.1 Averaging Approximation 13
2.3.2 Small-Signal AC Model 13
2.3.3 Converter Transfer Function 16
2.4 Conventional Control Mechanism 18
2.4.1 Voltage-Mode Control 18
2.4.2 Current-Programmed Control 18
3 System Design of Digitally Controlled DC-DC Buck Converter 20
3.1 Quantization Effects 20
3.1.1 Resolution Criterion in Steady-State Operation 21
3.1.2 Resolution Criterion in Dynamic Operation 22
3.2 Analysis of Voltage-Mode Control 23
3.2.1 Control-to-Output Transfer Function 24
3.2.2 PID Controller Design 25
PD Controller 27
PI Controller 28
Bilinear Transformation 29
Frequency Warping 30
Bilinear Transformation with Frequency Prewarping 31
3.2.3 Voltage-Mode Feedback System Analysis 33
3.2.4 Analog-to-Digital Converter Behavioral Model 37
3.2.5 Digital Pulse-Width Modulator Behavioral Model 39
3.2.6 Complete Voltage-Mode Buck Converter Behavioral Model 41
3.3 Analysis of Current-Mode Control 43
3.3.1 Current Control Law 43
3.3.2 Current-Mode Controller Small-Signal Model 46
3.3.3 Current-Mode Feedback System Analysis 51
3.3.4 Digital Current Sensor Behavioral Model 55
3.3.5 Complete Current-Mode Buck Converter Model 56
4 Circuit Design of Digitally Controlled Current-Mode DC-DC Buck Converter 60
4.1 Delay-Line Analog-to-Digital Converter 60
4.1.1 Propagation Delay of Delay Cell 62
4.1.2 Input Differential Stage 63
4.1.3 Resolution of Delay-Line ADC 63
4.1.4 Conversion Time of Delay-Line ADC 65
4.2 Digital PID Controller 65
4.3 Counter-Comparator Digital Pulse-Width Modulator 67
4.4 Successive-Approximation Digital Current Sensor 69
4.4.1 Operation Principles 70
4.4.2 Design Considerations 73
Sampling Clock for S/H Circuit 73
Clock for SAR Control Logic 74
Unit Current of Current Source Array 74
4.4.3 Circuit Implementations 75
Folded Flipped Voltage Follower 75
S/H Circuit 75
Cascode Current Source 76
Latched Comparator 76
SAR Control Logic 78
4.5 Predictive Current Control Law 78
4.6 Adaptive Dead-Time Controller 79
4.6.1 Operation Principles 80
4.6.2 Dead-Time Detector 81
4.6.3 Finite-State Machine 82
4.6.4 Dead-Time Adjustor 82
4.7 Soft-Start Circuit 83
4.8 Bandgap Voltage Reference, Current Reference, and Bias Circuits 84
4.8.1 Bandgap Voltage Reference 85
4.8.2 Current Reference 88
4.8.3 Bias Circuit 89
5 Simulation Results 91
5.1 Circuit Simulation 91
5.2 System Simulation 92
5.2.1 Static Response 92
Power Conversion Efficiency 92
Load Regulation 93
Line Regulation 94
5.2.2 Dynamic Response 94
Load Transient Response 94
Line Transient Response 97
5.3 Summary 99
6 Conclusions and Future Work 101
6.1 Conclusions 101
6.2 Future Work 101
6.2.1 Calibration of Delay-Line ADC 101
6.2.2 High-Resolution, Low- Area, Low- Power DPWM 102
6.2.3 Dual-Mode Modulation 102
References 104
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指導教授 薛木添(Muh-Tian Shiue) 審核日期 2014-7-8
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