博碩士論文 995201041 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:16 、訪客IP:3.231.102.4
姓名 黃志偉(Chei-Wei Huang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於電容陣列區塊之維持良率的皇后比例切割法
(QRC-CABC: A Yield-aware Placement with Queen Ratio Cutting for the Capacitor Array Block Creator)
相關論文
★ E2T-iSEE:應用於事件與情感狀態轉移排程器之編輯★ “偶”:具情感之球型機器人
★ 陣列區塊電容產生器於製程設計套件之評量★ 應用於數位家庭整合計畫影像傳輸子系統之設計考量與實現
★ LED 背光模組靜電放電路徑★ 電阻串連式連續參考值產生器於製程設計套件之評量
★ 短篇故事分類與敘述★ 延伸考慮製程參數相關性之類比電路階層式變異數分析器
★ 以電子電路觀點對田口式惠斯登電橋模擬實例的再分析★ 應用於交換電容ΔΣ調變電路之電容排列良率自動化擺置平台
★ 陣列MiM電容的自動化佈局★ 陣列MiM電容的平衡接點之通道繞線法
★ 氣象資訊達人★ 嵌入式WHDVI多核心Forth微控制器之設計
★ 應用於電容陣列區塊之維持比值良率的通道繞線法★ 使用於矽穿孔耦合分析之垂直十字鏈基板結構
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 ( 永不開放)
摘要(中) 近年來,隨著半導體製程技術的進步,製程變動(process variation)所造成元件之間的不匹配(mismatch)越來越嚴重,這代表類比電路設計上的複雜度與時間成本越來越高,佈局的自動化設計便成為電路設計過程中的關鍵角色。在現今多數的類比數位電路之中,像是類比數位/數位類比轉換器或濾波器等等,其性能都取決於準確的電容比值。所以,如何達到準確的電容比值就成為一個很重要的議題。而為了達到精確的電容比值,設計上會以並聯多顆較小的單位電容來取代一顆大電容,並利用空間相關性來解決製程變動所帶來的問題。其中,要切割成多少顆單位電容及如何擺放在電容陣列就成為佈局擺置自動化中非常重要的一環。 本論文提出一種應用於電容陣列區塊佈局之維持良率的皇后比例切割法的電容陣列佈局方法。我們將電容分成三大類來進行擺放,其一為直接擺放的皇后電容,其二為優先考慮最後擺放的貼身婢女電容,其三為最後考慮優先擺放的孚護騎士電容。此外,還特別制定了一個燈塔孚護機制,用來加入適當的空乏電容完成擺放。運用此方法在電容擺置上就能達到高分散性(dispersion)、耗時少且精確度高的電容陣列佈局。最後針對特定電路的特定電容組成的陣列進行比較。佈局完成後再透過Monte Carlo方法進行驗證,結果顯示電容比的匹配度提高且電路的良率提升。
摘要(英) As the advancement of semiconductor process technology, the process variation will be more and more serious in device mismatch for the analog integrated circuits. There are several placement algorithms presented to improve the capacitance ratio matching due to spatial correlation. In this thesis, a new yield-aware placement, named queen ratio cutting (QRC), is proposed for the capacitor array block creator (CABC). In QRC, there are four types of target capacitors to be assigned the position: queens, servant-girls, protection knights and Rooks. Queens are directly placed according to the rule of N-Queens Problem. Servant-girls are preferential considered and last placed. Protection knights are last considered and preferential placed. Rook assignment is to solve the dummy remainders in capacitor array. QRC is implemented and integrated in CABC. Several different continuous ratios are used as benchmarks to test the performance. It is shown that QRC reaches the better ratio yield with less area, where each ratio must be within 3-percent deviation.
關鍵字(中) ★ 電容陣列
★ 電容擺放
關鍵字(英) ★ capacitor array
★ capacitor placement
論文目次 中文摘要 ............................................................................................................ i
Abstrast ............................................................................................................. ii
致謝 ................................................................................................................. iii
目錄 ................................................................................................................. iv
圖目錄 ............................................................................................................. vi
表目錄 ........................................................................................................... viii
Chapter 1. 緒論 ........................................................................................... 1
1.1動機與背景 ......................................................................................... 1
1.2論文組織 ............................................................................................. 3
Chapter 2. 電容佈局設計的概念 ................................................................ 4
2.1電容之簡介 ......................................................................................... 4
2.2電容不匹配的原因 .............................................................................. 7
2.3電容匹配的規則 .................................................................................. 9
Chapter 3. 電容陣列的擺放 ...................................................................... 12
3.1共質心(Common-Centroid) ............................................................... 12
3.2空間相關性(Spatial Correlation) ........................................................ 15
3.2.1相關性(Correlation)與元件不匹配(Mismatch) ....................... 18
3.2.2電容比值的變異數與分散性 .................................................. 20
3.3皇后比例切割法(Queen Ratio Cutting) ............................................. 22
3.3.1皇后問題 ................................................................................. 22
v
3.3.2 皇后比例切割法的設計流程 ................................................. 25
3.3.3燈塔孚護機制 ......................................................................... 28
Chapter 4. 實驗結果與分析 ...................................................................... 32
4.1單一電容比的實現 ............................................................................ 33
4.2電容連比的實現 ................................................................................ 36
4.3二階濾波器的電路實現 .................................................................... 33
Chapter 5. 結論 ......................................................................................... 43
參考文獻 ......................................................................................................... 44
參考文獻 [1] X. Jinjun, V. Zolotov, and H. Lei, “Robust Extraction of Spatial Correlation,” IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, pp. 193-202, Apr. 2007.
[2] A. Hastings and R. A. Hastings, The Art of Analog Layout, Prentice Hall, 2000.
[3] M. J. McNutt, S. LeMarquis, and J. L. Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE J. Solid-State Circuits, pp.611-616, May 1994.
[4] P-W. Lou, J-E. Chen, C-L Wey, L-C. Cheng, J-J. Chen, and W-C. Wu,”Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, Iss. 11, pp. 2097-2101, Nov. 2008.
[5] D. Sayed and M. Dessouky, “Automatic generation of common-centroid arrays with arbitrary capacitance ratio,” in Proc. Design Autom. Test Eur.Conf. Exhibit., pp. 576–580, Mar. 2002.
[6] J.-E Chen, P.-W. Luo, and C.-L. Wey, “Placement optimization for yield improvement of switched-capacitor analog integrated circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,vol. 29, no. 2, pp. 313-318, Feb. 2010.
[7] C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang, and S.-J. Chang, “Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits,” in Proc. ACM/IEEE DAC, 2011, pp. 528-533.
[8] C.L. Wey, J.E. Chen, C.-C. Huang, and P.-W. Luo, “Yield-Driven Common-Centroid Capacitor Placements for Mixed-Signal/Analog Integrated Circuits,” Proc. of Int’l Workshop on Design Automation on Analog/Mixed-signal Integrated Circuits, San Jose, CA, Nov. 8, 2012.
[9] D. Khalil, M. Dessouky, V. Bourguet, M. M. Louerat, A. Catheline, and H. Ragai, “Evaluation of Capacitance Ratios in Automated Accurate Common-Centroid Capacitance Arrays,” Proceedings of the 6th ISQED, March 2005, pp. 143-147.
45
[10] H. Masuda, “Challenge: Variability Characterization and Modeling for 65- to 90-nm Processes,” IEEE Custom Integrated Circuits Conference 2005.
[11] L. Zhang, R. Raut, Y. Jiang, and U. Kleine. “Placement algorithm in analog-layout designs,” IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, pp.1889-1903, Oct. 2006.
[12] M.-F. Lan, A. Tammineedi and R. Geiger. “Current Mirror Layout Strategies for Enhancing Matching Performance,” Analog Integrated Circuit and Signal Processing, Kluwer Academic Publishers, pp. 9-26, Jul. 2001.
[13] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, pp.1433-1439, Oct 1989.
[14] B. Razavi, Design of Analog CMOS Integrated Circuits, Mcgraw-Hill, 2001.
[15] C. S. G. Conroy, W. A. Lane, and M. A. Moran, “Statistical Design Techniques for D/A Converters,” IEEE Journal of Solid-State Circuits, pp. 1118-1128, Aug 1989
[16] K.R. Laker and W.M. Sansen, Design of Analog Integrated Circuits and Systems, McGraw Hill, 1994.
指導教授 陳竹一(Jwu-E Chen) 審核日期 2013-11-28
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明