應用於無線個人區域網路系統之低雜訊放大器設計與實現

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吳偲銘(Shi-Ming Wu) 查詢紙本館藏

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電機工程學系

論文名稱

應用於無線個人區域網路系統之低雜訊放大器設計與實現
(Design and Implementation of Low Noise Amplifiers for WPAN Applications)

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摘要(中)

在無線收發機當中，低雜訊放大器為一不可或缺的電路區塊。它是射頻前端中之接收鏈最前端的主動電路，其功能為在盡量不增加雜訊的狀況下將輸入訊號放大。接收鏈當中最前端電路的雜訊指數與增益主導了整個接收鏈整體的雜訊表現。因此設計一具有低雜訊指數與高增益的放大器是相當必要的。本論文將探討應用於無線個人區域網路系統之低雜訊放大器設計與實現。
我們設計了兩個低雜訊放大器電路。第一個電路是應用於IEEE 802.15.3c、中心頻為60 GHz之低雜訊放大器，並且透過TSMC 90-nm CMOS製程去實現。此電路採用串疊架構去實現，並在串疊架構中加入一雜訊抑制電感以達到降低雜訊與提升穩定度的功能。該電路在61.4 GHz時具有最佳增益13.4 dB，雜訊指數為6.02 dB，3-dB頻寬為12.4 GHz （54.9–67.3 GHz），功耗為29 mW；雜訊指數之量測最低值出現在67.5 GHz，其值為4.95 dB。電路於60 GHz之輸入P1dB為−9 dBm。
第二個電路為應用於IEEE 802.15.3a超寬頻之可調式低雜訊放大器，且透過WIN 0.15-μm pHEMT製程實現。電路架構採用兩級串接架構去實現，並使用以變容二極體為基礎的可調式匹配網路以達到操作頻率可調的功能。該電路在可調頻率（6.5–8.5 GHz）範圍內，其增益介於6.87–8.3 dB，雜訊指數介於4.4–5.5 dB，電路於7.5 GHz之輸入P1dB為−6 dBm，功耗為16.5 mW。

摘要(英)

In wireless transceivers, low noise amplifier (LNA) is an indispensable circuit block. It is the first active circuit in the receiving chain of a radio frequency (RF) front-end. The function of a LNA is to amplify the input signal while keeping the added noise as small as possible. Because the noise performance of a receiver is dominated by the noise figure and the gain of the first few stages, it is therefore necessary to design amplifiers with low noise figure and high gain. In this thesis, the design and implementation of two LNAs for WPAN applications are presented.
The first LNA is designed for IEEE 802.15.3c frequency band, centered at 60 GHz, and is implemented using TSMC 90-nm CMOS process. In this circuit, cascode topology is adopted. Between the common-source and common-gate stages, an inductor is added to reduce the noise figure and enhances the stability of the amplifier. The amplifier has a maximum gain of 13.4 dB at 61.4 GHz with a noise figure of 6.02 dB. The 3-dB bandwidth is 12.4 GHz (54.9–67.3 GHz) and the DC power consumption is 29 mW. Minimum noise figure of 4.95 dB is observed at 67.5 GHz. The input P1dB at 60 GHz is −9 dBm.
The second LNA is designed for IEEE 802.15.3a ultra-wide band (UWB) applications and is implemented using WIN 0.15-μm pHEMT process. The circuit is a two-stage amplifier with varactor-diode-based tunable matching networks to achieve tuning of the operating frequency. In the operating frequency range (6.5–8.5 GHz), the gain ranges from 6.87 dB to 8.3 dB whereas the noise figure is from 4.4 dB to 5.5 dB. The input P1dB at 7.5 GHz is −6 dBm and the DC power consumption is 16.5 mW.

關鍵字(中)

★ 低雜訊放大器
★ 射頻
★ 可調式
★ 無線個人區域網路

關鍵字(英)

★ 60 GHz
★ tunable
★ WPAN
★ LNA
★ RF

論文目次

摘要 I
Abstract II
誌謝 III
目錄 V
圖目錄 VII
表目錄 X
第一章緒論 1
1–1 研究動機 1
1–2 文獻回顧 4
1–3 論文架構 6
第二章應用於60 GHz之低雜訊放大器 7
2–1 簡介 7
2–2 低雜訊放大器設計與電路架構介紹 9
2–2–1 設計雜訊抑制電感 10
2–2–2 完整電路架構 14
2–3 電路模擬與量測結果 18
2–3–1 量測方式介紹 19
2–3–2 模擬與量測結果比較 22
2–3–3 量測與偵錯結果比較 26
2–4 結果與討論 33
第三章應用於超寬頻之可調式低雜訊放大器 35
3–1 簡介 35
3–2 可變電感實現與分析 37
3–2–1 以LC串聯實現可變電感 38
3–2–2 以LC並聯實現可變電感 40
3–3 電路設計流程與電路架構介紹 42
3–3–1 尋找電晶體參數 42
3–3–2 設計源極退化電感 44
3–3–3 設計輸入匹配 46
3–3–4 設計級間匹配 52
3–3–5 設計輸出匹配 57
3–3–6 完整電路架構 61
3–4 電路模擬與量測結果 64
3–4–1 量測方式介紹 65
3–4–2 模擬與量測結果比較 66
3–4–3 量測與偵錯結果比較 71
3–5 結果與討論 76
第四章結論與未來展望 78
參考文獻 80

參考文獻

[1] B. Razavi, “A 60GHz direct-conversion CMOS receiver,” IEEE International Solid-State Circuits Conference Digest, pp. 400–401, Feb. 2005.
[2] S. Emami, C. H. Doan, A. M. Niknejad, and R. W. Broderson, “A 60-GHz down-converting CMOS single-gate mixer,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 163–166, Jun. 2005.
[3] D. Huang, W. Hant, N.-Y. Wang, T. W. Ku, Q. Gu, R. Wong, and M.-C. F. Chang, “A 60 GHz CMOS VCO using on-chip resonator with embedded artificial dielectric for size, loss, and noise reduction,” IEEE International Solid-State Circuits Conference Digest, pp. 314–315, Feb. 2006.
[4] T. Yao, M. Gordon, K. Yau, M. T. Yang, and S. P. Voinigescu, “60-GHz PA and LNA in 90-nm RF CMOS,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 147–150, Jun. 2006.
[5] B. Razavi, “A millimeter-wave CMOS heterodyne receiver with on-chip LO and divider,” IEEE International Solid-State Circuits Conference Digest, pp. 188–189, Feb. 2007.
[6] S. Emami, C. H. Doan, A. M. Niknejad, and R. W. Broderson, “A highly-integrated 60-GHz CMOS front-end receiver,” IEEE International Solid-State Circuits Conference Digest, pp. 190–191, Feb. 2007.
[7] T. Mitomo, R. Fujimoto, N. Ono, R. Tachibana, H. Hoshino, Y. Yoshihara, Y. Tstustumi, and I. Seto, “A 60-GHz CMOS receiver with frequency synthesizer,” IEEE VLSI Circuits Symposium, pp. 172–173, Jun. 2007.
[8] A. Parsa and B. Razavi, “A 60-GHz CMOS receiver using a 30-GHz LO,” IEEE International Solid-State Circuits Conference Digest, pp. 190–191, Feb. 2008.
[9] B. Afshar, Y. Wang, and A. M. Niknejad, “A robust 24-mW 60-GHz receiver in 90 nm standard CMOS,” IEEE International Solid-State Circuits Conference Digest, pp. 182–183, Feb. 2008.
[10] M. Tanomura, Y. Hamada, S. Kishimoto, M. Ito, N. Orihashi, K. Maruhashi, and H. Shimawaki, “TX and RX front ends for the 60-GHz band in 90 nm standard bulk CMOS,” IEEE International Solid-State Circuits Conference Digest, pp. 558–559, Feb. 2008.
[11] C. Weyers, P. Mayr, J. W. Kunze, and U. Langmann, “A 22.3 dB voltage gain 6.1 dB NF 60 GHz LNA in 65 nm CMOS with differential output,” IEEE International Solid-State Circuits Conference Digest, pp. 192–193, Feb. 2008.
[12] B. Razavi, “A millimeter-wave circuit technique,” IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2090–2098, Sep. 2008.
[13] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier ,” IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp.745-759, May 1997.
[14] Y.-C. Chen and C.-N. Kuo, “A 6-10-GHz ultra-wideband tunable LNA,” in Proceedings of IEEE International Symposium on Circuits and Systems, vol. 5, pp. 5099–5102, May 2005.
[15] C. Fang, C. L. Law, and J. Hwang, “A 3.1-10.6 GHz ultra-wideband low noise amplifier with 13-dB gain, 3.4-dB noise figure, and consumes only 12.9 mW of DC power,” IEEE Microwave Wireless Component Letters, vol. 17, no. 4, pp. 295–297, Apr. 2007.
[16] B. Heydari, M. Bohsali, E. Adabi, and A. M. Niknejad, “Low-power mm-wave components up to 104 GHz in 90 nm CMOS,” IEEE International Solid-State Circuits Conference Digest, pp. 200–597, June 2007.
[17] H.-K. Cha, M. K. Raja, X. Yuan, and M. Je, “A CMOS medradio receiver RF front-end with a complementary current-reuse LNA,” IEEE Transactions on Microwave Theory and Techniques, vol. 59, pp. 1846–1854, July 2011.
[18] A. Siligaris, C. Mounet, B. Reig, P. Vincent, and A.Michel, “CMOS SOI technology for WPAN application to 60 GHz LNA,” IEEE Integrated Circuit Design and Technology and Tutorial, pp. 17–20, June 2008.
[19] K. Kang, J. Brinkhoff, and F. Lin, “A 60 GHz LNA with 18.6 dB gain and 5.7 dB NF in 90 nm CMOS,” IEEE International Conference on Microwave and Millimeter Wave Technology, pp. 164–167, May 2010.
[20] S. Pellerano, Y. Palaskas, and K. Soumyanath, “A 64 GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS,” ESSCIRC Solid-State Circuits Conference, pp. 352–355, Sep. 2007.
[21] C. H. Doan, S. Emami, A. M. Niknejad, and R. W. Brodersen, “Millimeter-wave CMOS design,” IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 144–155, Jan. 2005.
[22] B. Park, S. Choi, and S. Hong, “A low-noise amplifier with tunable interference rejection for 3.1- to 10.5-GHz UWB System,” IEEE Microwave Wireless Component Letters, vol. 20, no. 1, pp. 40–42, Jan. 2010.
[23] Q. Li, Y. P. Zhang, and J. S. Chang, “An inductorless low-noise amplifier with noise cancellation for UWB receiver front-end,” IEEE Asian Solid-State Circuits Conference, no. 4, pp. 267–270, Nov. 2006.
[24] T. K. K. Tsang and M. N. El-Gamal, “Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNA,” IEEE International Symposium on Circuits and Systems, vol. 4, pp. 795–798, Aug. 2002.
[25] C.-T. Fu, C.-L. Ko, C.-N. Kuo, and Y.-Z. Juang, “A 2.4-5.4-GHz wide tuning-range CMOS reconfigurable low-noise amplifier,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 12, pp. 2754–2763, Dec. 2008.
[26] F. Ellinger, H. Jackel, and W. Bachtold, “Varactro-loaded transmission-line phase shifter at C-band using lumped elements,” IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 4, pp. 1135–1140, Apr. 2003.
[27] A. Borgioli, Y. Liu, A. S. Nagra, and R. A. York, “Low-loss distributed MEMS phase shifter,” IEEE Microwave and Guided wave Letters, vol. 10, no. 1, pp. 7–9, Jan. 2000.
[28] M. Sazegar, Y. Zheng, H. Maune, C. Damm, X. Zhou, J. Binder, and R. Jakoby, “Low-cost phase-array antenna using compact tunable phase shifters based on ferroelectric ceramics,” IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 5, pp. 1265–1273, May 2011.
[29] Y. Lu, “RF MEMS devices and their applications in reconfigurable RF/microwave circuits,” Ph.D. dissertation, The University of Michigan, An Arbor, MI, USA, 2005.
[30] Y.-C. Lin, “Design and fabrication of distributed analog phase shifters,” Master dissertation, National Central University, 2011.
[31] F. Gutierrez, S. Agarwal, K. Parrish, and T. S. Rappaport, “On-chip integrated antenna structures in CMOS for 60 GHz WPAN systems,” IEEE Journal on Selected Areas in Communications, vol. 27, pp. 1367–1378, Oct. 2009.
[32] B. Razavi, “Design of analog CMOS integrated circuits,” McGraw-Hill, 2001
[33] B. J. Huang, K. Y. Lin, and H. Wang, “Millimeter-wave low power and miniature CMOS multicascode low-noise amplifiers with noise reduction topology,” IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. 12, pp. 3049–3059, Dec. 2009.
[34] I. Song, J. Jeon, H.-S. Jhon, J. Kim, B.-G. Park, J.-D. Lee and H. Shin, “A simple figure of merit of RF MOSFET for low-noise amplifier design,” IEEE Electron Device Letters, vol. 29, pp. 1380–1382, Dec. 2008.
[35] S.-H. Weng, C.-H. Lin, H.-Y. Chang, and C.-C. Chiong, “Q-band low noise amplifier using a 0.15μm MHEMT process for broadband communication and radio astronomy applications,” 2008 IEEE MTT-S International Microwave Symposium Digest, pp. 455–458, June 2008.
[36] Y. Yu, P. G. M. Baltus, A. Graauw, E. V. D. Heilden, C. S. Vaucher, and A. H. M. Roermund, “A 60 GHz phase shifter integrated with LNA and PA in 65 nm CMOS for phased array systems,” IEEE Journal of Solid-State Circuits, vol. 45, no. 9, pp. 1697–1709, Sep. 2010.

指導教授

傅家相(Jia-Shiang Fu)

審核日期

2012-8-8

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