平面式鍺量子點單電子電晶體之研製與特性分析

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姓名

邱俊閔(Chun-Min Chiou) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

平面式鍺量子點單電子電晶體之研製與特性分析
(Fabrication and Electrical Characterizations of Germanium QD Single Electron Transistor in Planar Structure)

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摘要(中)

單電子電晶體既具有高電荷靈敏度以及低功率消耗之潛能優點，亦是元件尺寸不停微縮的趨勢下所因應而生之量子元件。本論文目的是藉由改進本研究室前一代平面式單電子電晶體之缺點，並且重新設計，進而改善元件電特性與提升良率。
在此篇論文中，我們將針對平面式的鍺量子點單電子電晶體的研製以及電流特性的分析作深入的探討研究。首先在製程上，我們先利用一奈米孔洞的製作來達成量子點的精確定位，之後利用選擇性熱氧化的方式在孔洞中心形成單顆的鍺量子點並且有對稱的穿隧介電層。接著使用電子束微影並搭配電極圖案的設計去定義元件之各端電極，簡化了以往製作單電子電晶體時因為源/汲電極與閘電極是分別去定義與形成，會有比較複雜之製程步驟。最後我們利用分析訊號以及蝕刻的方式來去大量降低在兩道微影對準製程時之不確定性，使平均對準偏移量控制得以在15 nm以內。在溫度為120 K至80 K的電性量測下，元件展現出相當清晰並且有可意義的庫倫震盪現象。最後我們分別從結構上以及量測結果上估算單電子電晶體特性參數，並進行比較與分析。

摘要(英)

Single-electron transistors (SET) offer great potential for high charge sensitivity and low-power consumption. Besides, it’s a rational quantum device which conforms to the historical trend of the device scaling. This thesis has redesigned and reformed the SET device originated from our group before for the purpose to promote the yield rate and advance the electrical performance.
In this thesis, we demonstrated the fabrication and electrical characterizations of germanium quantum dot (Ge QD) in planar structure. We are able to position and number Ge QDs by means of fabricating a nano-cavity. After thermal oxidizing the SiGe polygonal in the nano-cavity, it produced a single Ge QD in the center with symmetrical tunneling junction. Instead of quite complicated SET process of the past that made Gate and S/D to be defined respectively, all electrodes are formed together for this SET device by particularity patterning with electronic beam lithography. Additionally, through suitable signal processing to alleviate the uncertainty of lithography alignment, we successfully reduce miss alignment to less than 15 nm in average.
The fabricated Ge QD SET exhibits reliable and clear Coulomb oscillation behaviors under gate and drain modulation at T = 80 K－120 K. In addition, we make some preliminary estimates from device structure, and compare them with measurement data.

關鍵字(中)

★ 單電子電晶體
★ 鍺量子點
★ 電子束微影

關鍵字(英)

論文目次

中文摘要 i
英文摘要 ii
致謝 iv
目錄 vi
圖目錄 vii
表目錄 xiii
第一章、簡介與研究動機
1-1 論文的整體架構 1
1-2 單電子電晶體的誕生 1
1-3 近年來各團對於單電子電晶體之研究 3
1-4 研究動機 10

第二章、平面式單電子電晶體元件設計與關鍵製程開發
2-1　前言 26
2-2 元件設計與關鍵製程開發 27
I. 奈米孔洞的製作 27
II. 各端電極微影製程 28
III. 電子束微影對準實驗 31

第三章、元件製作流程
3-1 前言 43
I. Buffer layer製作 43
II. 定義主動區 43
III. 定義奈米孔洞 44
IV. 沉積Si3N4 spacer形成穿隧位障 44
V. 回蝕多晶矽鍺合金並氧化形成鍺量子點 45
VI. 奈米孔洞結構檢視 45
VII. 電子束微影定義各端電極 45
VIII. 離子佈值與回火形成半導體電極 46
IX. 後段製程 46
第四章、元件電流特性分析與討論
4-1　單電子電晶體操作原理 53
4-2　量測儀器與量測參數預期說明 54
4-3　元件ID-VD電流特性 56
4-3.1　常溫（300 K）普查情況 56
4-3.2　ID-VDS 降溫量測 ( 120, 100, 80 K ) 57
4-4　元件ID-VG電流特性 60
4-5　元件量測參數分析討論 62
4-6　結論 65
第五章、總結與未來展望 74
參考文獻 75

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指導教授

李佩雯(Pei-Wen Li)

審核日期

2013-1-16

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