博碩士論文 995201104 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:16 、訪客IP:3.95.131.208
姓名 廖彥涵(Yen-han Liao)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 微波毫米波寬頻振盪器與鎖相迴路之研製
(Microwave and Millimeter-wave Broadband Oscillator and Phase-locked Loop)
相關論文
★ 微波及毫米波切換器及四相位壓控振盪器整合除三 除頻器之研製★ 微波低相位雜訊壓控振盪器之研製
★ 高線性度低功率金氧半場效電晶體射頻混波器應用於無線通訊系統★ 砷化鎵高速電子遷移率之電晶體微波/毫米波放大器設計
★ 微波及毫米波行進波切換器之研製★ 寬頻低功耗金氧半場效電晶體 射頻環狀電阻性混頻器
★ 微波與毫米波相位陣列收發積體電路之研製★ 24 GHz汽車防撞雷達收發積體電路之研製
★ 低功耗低相位雜訊差動及四相位單晶微波積體電路壓控振盪器之研究★ 高功率高效率放大器與振盪器研製
★ 微波與毫米波寬頻主動式降頻器★ 微波及毫米波注入式除頻器與振盪器暨射頻前端應用
★ 寬頻主動式半循環器與平衡器研製★ 雙閘極元件模型與微波及毫米波分佈式寬頻放大器之研製
★ 銻化物異質接面場效電晶體之研製及其微波切換器應用★ 使用達靈頓對之單晶微波及毫米波寬頻電路
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 近年來無線通訊產業快速發展,關鍵技術日趨成熟,但是射頻無線積體電路的製作價格仍然偏高,為了降低製作成本及整合數位類比電路於單一晶片上,採用低價格的互補式金屬氧化物半導體製程來開發設計,已是未來的發展趨勢。在無線通訊的收發機中,低相位雜訊的壓控振盪器是不可或缺的元件,如何設計高頻率並同時具有低相位雜訊的振盪器是一個值得探討的主題。鎖相迴路則是穩定壓控振盪器輸出頻率的方法之一,將注入鎖定技術應用於振盪器、除頻器、鎖相迴路與等主動電路,可以改善本地振盪源之電路性能。在通訊系統中,常將訊號分成I/Q兩通道,增加其適用的頻寬,因此收發電路中常需使用四相位正交訊號輸出的振盪器,才可進行調變或解調。本論文內容分成四部分,第二章設計三種應用於K頻段的寬頻差動振盪器,第三章設計注入鎖定倍頻器,第四章提出新型四相位壓控振盪器,第五章提出注入鎖定除六除頻器並應用於K頻段鎖相迴路,並對振幅及相位誤差作分析探討。
第二章為使用穩懋砷化鎵為材質之異質接面雙極性電晶體,和假晶格高速電子移動率電晶體製程,設計三種應用於K頻段的低功耗低相位雜訊的差動壓控振盪器,包括基本的共基極差動振盪器,將異質接面雙極性電晶體疊接假晶格高速電子移動率電晶體的共射極差動振盪器,以及使用主動負載共射極差動振盪器,對電路做負阻及頻寬的分析。三種電路可調頻寬的百分比分別達到38.3%、22%、31.3%,晶片面積均為1×1 mm2,與近年文獻比較均有較佳的頻寬及優化指數的表現。
第三章為注入鎖定倍頻器的設計與分析。由於高頻特性受限於元件,直接實現一高頻壓控振盪器是不容易的,此電路利用較低頻的振盪器串接倍頻器在想要的頻段獲得訊號,並使用台積電提供的0.18 μm矽鍺雙載子互補金氧半導體製程實現。由量測結果得知,可調頻寬範圍17.08至18.37 GHz,其輸出功率均高於-8.4 dBm,輸出頻率為18.4 GHz時,偏移中心頻 1 MHz 量測之輸出相位雜訊為-99.8 dBc/Hz,鎖定頻寬有1.4 GHz,直流功率消耗為7 mW,晶片面積為0.49×0.73 mm2。
第四章介紹四相位壓控振盪器的原理與架構,並提出新型的四相位振盪器,同時說明其設計概念及直接量測相位、振幅誤差的方法。使用台積電90 nm CMOS製程實現了K頻段使用變壓器回授及閘極調變架構之壓控振盪器,振盪頻率可調範圍為1.7 GHz,輸出功率為-9.6 dBm,輸出頻率為25.07 GHz時,偏移中心頻 1 MHz 量測之輸出相位雜訊為-98.6 dBc/Hz,量測到最小的振幅誤差為0.55 dB,相位誤差為0.28°,直流功率消耗為16.15 mW,晶片面積為0.74×0.89 mm2。優位指數為-174.4 dBc/Hz。
第五章介紹基本除頻器架構以及設計原理,同時採用台積電提供的0.18 μm 互補式金屬氧化物半導體製程實現一個除五注入鎖定除頻器,量測最大鎖定頻寬為1.1 GHz。將此注入鎖定除頻器整合至鎖相迴路系統,包含注入鎖定壓控振盪器、相位頻率偵測器、電荷幫浦、迴路濾波器及除頻鏈,同樣是使用台積電0.18 μm互補式金屬氧化物半導體製程實現,其鎖定頻率範圍為22.09至22.19 GHz,未注入前,鎖定頻率為22.15 GHz 時,在偏移中心頻 1 MHz 量測之輸出相位雜訊為-104 dBc/Hz,注入後,當鎖定頻率為22.15 GHz 時,在偏移中心頻 1 MHz 量測之輸出相位雜訊為-130 dBc/Hz,迴路中使用注入鎖定振盪器改善了鎖相迴路的相位雜訊,提供品質更好的本地振盪源。此電路總共直流消耗為102 mW,晶片面積為1.06×1.395 mm2。
摘要(英) For a transceiver in wireless communication, the low phase noise local oscillator (LO) source is an indispensable element, since it is an important issue for designing a high-frequency and low phase noise LO source is an important issue. The phase-locked loop (PLL) is one of the methods to stabilize the output frequency of the voltage-controlled oscillator (VCO). In order to provide system with a stable and low phase noise LO source for the microwave and millimeter wave (MMW) system, an injection-locked technique can be adopted to enhance the operation frequency for many active circuits, such as oscillator, frequency divider, PLL, and frequency multiplier. A key building block in the LO source is the VCO with quadrature outputs. The quadrature VCO (QVCO) is needed for I/Q modulation or demodulation.
In Chapter 2, three K-band differential VCOs, including a conventional common-base VCO, a cascode commom-emitter VCO and a conventional commom-emitter VCO with active load, have been designed using WIN Semiconductors 0.5-μm PHEMT and 2-μm HBT technology. The negative resistance of the HBT-HEMT cascode VCO is analyzed. The tuning bandwidth of the differential VCOs are 38.3%、22% and 31.3%. The CB differential VCOs demonstrates the widest bandwidth among the relevant literatures.
The design and analysis of an injection-locked oscillator (ILO) is presented in Chapter 3. Simulated normalized third harmonic currents of the frequency pre-generator as a function of base current, and select the base current for higher frequency conversion efficiency while maintaining oscillation. The ILO with a locking range of 1.4 GHz is realized using TSMC 0.18-μm SiGe BiCMOS process. The measured maximum output frequency is 18.37 GHz.
In the Chapter 4, we used TSMC 90-nm CMOS process to realize a K-band VCO with transformer-feedback and gate-modulation techniques. The analysis for generating quadrature is presented in detailed manner.The measured oscillation frequency is from 23.4 to 25.1 GHz. The measured phase noise is -98.6 dBc/Hz at 1-MHz offset. The dc power consumption is 16.15 mW and the RF output power is -9.6 dBm. The minimum I/Q phase and amplitude error are 0.28° and 0.55 dB, respectively. The VCO demonstrates a figure of merit (FOM) of -174.4 dBc/Hz.
The analysis and design of the ILFD are presented in Chapter 5. The divide-by-6 ILFD with a locking range of 1.1 GHz is fabricated using TSMC 0.18-μm CMOS process. Moreover, the proposed ILFD is applied to a fully integrated PLL, and the measured frequency of the PLL is from 22.09 to 22.19 GHz. The measured phase noise with injection signal is −130 dBc/Hz at 1 MHz offset. The dc power consumption is 102 mW. The inection-locked technique is used to improve the phase noise of the PLL. The conclusion is given in Chapter 6.
關鍵字(中) ★ 振盪器
★ 鎖相迴路
★ 正交振盪器
★ 注入鎖定
關鍵字(英) ★ voltage-controlled oscillator
★ Phase-lock loop
★ QVCO
★ Injection-locked
論文目次 摘要 1
ABSTRACT 3
目錄 5
圖目錄 8
表目錄 16
第一章 緒論 18
1.1 研究動機與背景 18
1.2 研究發展及現況 18
1.3 貢獻 19
1.4 論文架構 20
第二章 應用於K頻段之差動振盪器 22
2.1 簡介 22
2.2 電路架構設計與分析 23
2.2.1 振盪器架構簡介 24
2.2.2 Cascode架構負阻分析 30
2.2.3 其他設計參數 40
2.3 電路實現與量測結果討論 43
2.4 結論 54
第三章 注入式鎖定振盪器 56
3.1 簡介 56
3.2 倍頻器之優點與工作原理[38] 57
3.3 轉換效率增進的方法[38] 58
3.4 倍頻器電路模擬與分析 60
3.5 量測結果及討論 64
3.6 結論 75
第四章 閘極調變四相位輸出壓控振盪器 76
4.1 簡介 76
4.2 四相位輸出架構簡介 77
4.3 閘極調變四相位壓控振盪器設計與分析 84
4.3.1 電路架構 84
4.3.2 閘級調變耦合及四相位輸出-串聯法 85
4.3.3 閘級調變耦合及四相位輸出-並聯法 89
4.3.4 變壓器回授 96
4.3.5 偏壓模擬 101
4.3.6 S參數模擬 102
4.4 量測結果與討論 104
4.5 結論 111
第五章 應用於K頻段鎖相迴路之注入鎖定除頻器 114
5.1 簡介 114
5.2 除頻器架構概述 115
5.3 除六注入鎖定除頻器 121
5.3.1 電路設計與分析 121
5.3.2 鎖定頻寬分析[72] 124
5.4 電路實現與量測結果討論 128
5.5 應用於K頻段鎖相迴路 136
5.5.1 鎖相迴路簡介 136
5.5.2 電路設計與分析 137
5.5.2.1 注入鎖定振盪器 137
5.5.2.2 除頻器 140
5.5.2.3 相位頻率偵測器 142
5.5.2.4 電荷幫浦 143
5.5.2.5 迴路濾波器與迴路分析[96] 146
5.5.3 鎖相迴路實現與量測結果討論 151
5.6 結論 155
第六章 結論 157
參考文獻 159
參考文獻 [1] “Optimization of quadrature modulator performance,” Technical Notes and Articles,
RF Micro Devices Inc.
[2] 陳憲瑞,“無線寬頻系統之前端接收機與頻率合成器暨V頻段除頻器之研製”,民國96年7月。
[3] K.-H. Tsai, L.-C. Cho, J.-H. Wu, and S.-I. Liu, “3.5 mW W-band frequency divider with wide-locking-range in 90-nm CMOS technology,” in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 466–628.
[4] Y.-H. Wong, W.-H. Lin, J.-H. Tsai, and T.-W. Huang, “A 50-to-62 GHz wide-locking-range CMOS injection-locked frequency divider with transformer feedback,” in IEEE RFIC Symp. Dig. Papers, 2008, pp. 435–438.
[5] J.-C. Chien and L.-H. Lu, “A 40 GHz wide-locking-range frequency divider and low-phase-noise balanced VCO in 0.18-μm CMOS,” in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 544–621.
[6] S.-L. Jang, C.-F. Lee, and W.-H. Yeh, “A wide-locking-range ÷3 injection-locked frequency divider using linear mixer,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 7, pp. 390–392, Feb. 2010.
[7] X.-P. Yu et al., “A 3 mW 54.6 GHz divide-by-3 injection-locked frequency divider with resistive harmonic enhancement,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 9, pp. 575–577, Sep. 2009.
[8] S.-L. Jang and C.-W Chang, “A 90-nm CMOS LC-tank divide-by-3 injection locked frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 4, pp. 229–231, Apr. 2010.
[9] K. Yamamoto and M. Fujishima, “70 GHz CMOS harmonic injection-locked divider,” in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 2472–2481.
[10] M.-C. Chuang, J.-J. Kuo, C.-H. Wang, and H. Wang, “A 50 Ghz divide-by-4 injection lock frequency divider using matching method,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 5, pp. 344–346, May 2008.
[11] H.-H. Hsieh, H.-S. Chen, and L.-H. Lu, “A V-Band divide-by-4 direct injection-locked frequency divider in 0.18-μm CMOS,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 2, pp. 393–405, Feb. 2011.
[12] J. Hu and B. Otis, “A 3 μW, 400 MHz divide-by-5 injection-locked frequency divider with 56% lock range in 90-nm CMOS”, in IEEE RFIC Symp. Dig. Papers, pp. 665–668, 2008.
[13] B. Razavi, RF Microelectronics, Prentice Hall, 1998.
[14] Adel S. Sedra and Kenneth C. Smith, Microelectronic Circuits, Oxford, New York, pp. 1112-1113, 1998.
[15] F. Maloberti and M. Signorelli, “Quadrature waveform generator with enhanced
performances”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 56-57,
1998.
[16] H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,”
IEEE Journal of Solid-State Circuits, vol. 34, no. 6, pp. 813-821, June 1996.
[17] A. Rofougaran, G. Chang, J. J. Rael, J. Y.-C. Chang, M. Rofougaran, P. J. Chang, M. Djafari, J. Min, E. W. Roth, A. A. Abidi, and H. Samueli, “A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS—Part I: Architecture and transmitter design,” IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 515–534, Apr. 1998.
[18] C.-T. Lu, H.-H. Hsieh, and L.-H. Lu, “A low-power quadrature VCO and its application to a 0.6-V 2.4-GHz PLL,” IEEE Transactions on Circuits and Systems—I: Regular Papers, vol. 57, no. 4, pp. 793–802, Apr. 2010.
[19] K.-W. Cheng and D. J. Allstot, “A gate-modulated CMOS LC quadrature VCO,” in IEEE Radio Freq. Integrated Circuits Symp. Dig., 2009, pp. 267–270.
[20] P. Andreani, A. Bonfanti, L. Romanò, and C. Samori, “Analysis and design of a 1.8-GHz CMOS LC quadrature VCO,” IEEE J. Solid-State Circuits, vol. 37, pp. 1737–1747, Dec. 2002
[21] WIN Semiconductors, “0.5-μm InGaAs pHEMT enhancement/depletion-model device (E/D-mode) device model handbook,” ver.1.0.1, May, 2006.
[22] R. M. Weng and J. Y. Lin, “A 2.4 GHz low phase noise voltage controlled oscillator, ” Proceedings of Progress in Electromagnetics Research Symposium, eijing, 23-27 March 2009, pp. 546-550.
[23] H.-Y. Chang, Y.-S. Wu, and Y.-C. Wang, “A 38% tuning bandwidth low phase noise differential voltage controlled oscillator using a 0.5 μm E/D-pHEMT process,” IEEE Microwave and Wireless Comp. Lett. vol. 19, no. 07, pp. 467-496, July. 2009.
[24] J. Lin, K. Y. Chen, D. A. Humphrey, R. A. Hamm, R. J. Malik, A. Tate, R. F. Kopf, and R. W. Ryan, “Ka-band monolithic InGaAs/InP HBT VCO’s in CPW structure,” IEEE Microw. Guided Wave Lett., vol. 5, no. 11, pp. 379–381, Nov. 1995.
[25] K. Kamozaki, N. Kurita, W. Hioe, T. Tanimoto, H. Ohta, T. Nakamura, and H. Kondoh, “A 77 GHz T/R MMIC chip set for automotive radar systems,” in 1997 GaAs IC Symp. Dig., pp. 275-278.
[26] M. Klotz, and H. Rohling, “24-GHz radar sensors for automotive applications,” 2000 Microwave Radar and Wireless Communications Conference Dig., vol. 1, May 2000, pp. 359-362.
[27] B. Piernas, K. Nishikawa, T. Nakagawa, and K. Araki, “A compact and low-phase-noise Ka-Band pHEMT-based VCO,” IEEE Trans.Microw. Theory Tech., vol. 51, no. 3, pp. 778–783, Mar. 2003.
[28] S. Choi and K. Yang, “Low-voltage low-power K-band balanced RTD-based MMIC VCO,” in IEEE MTT-S Int. Dig., Jun. 2006, pp. 743–746.
[29] H.-C. Chiu, C.-C. Wei, C.-S. Cheng, and Y.-F. Wu, “Phase-noise improvement of GaAs pHEMT K-band voltage-controlled oscillator using tunable field-plate voltage technology,” IEEE Electron Device Lett., vol. 29, no. 5, pp. 426–429, May 2008.
[30] C.-C. Chiong, H.-Y. Chang, and M.-T. Chen, “Wide-bandwidth InGaP-GaAs HBT voltage-controlled oscillators in K- and Ku-band,” in Proceeding of Global Symposium on Millimeter ave (GSMM), Nanjing, Apr. 2008, pp. 185-188.
[31] C.-C. Chiong, H.-Y. Chang, M.-T. Chen, “Ka-band wide-bandwidth voltage-controlled oscillator in InGaP-GaAs HBT technology,” in European Microw. Integr. Circuit, Oct. 2008, pp. 358-361.
[32] Y.-J. E. Chen, W.-M. L. Kuo, Z. Jin, J. Lee, Y. V. Tretiakov, J. D. Cressler, J. Laskar, and G. Freeman, “A low-power Ka-band voltage-controlled oscillator implemented in 200-GHz SiGe HBT technology,” IEEE Trans. on Microwave Theory and Techniques, vol. 53, no. 5, pp. 1672-1681, May 2005.
[33] B. Jung and R. Harjani, “High-frequency LC VCO design using capacitive degeneration,” IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2359–2370, Dec. 2004.
[34] A. Scuderi, and G. Palmisano, “A low-phase-noise voltage-controlled oscillator for 17-GHz applications,” IEEE Microwave and Wireless Comp. Lett. vol. 16, no. 4, pp. 191-193, Apr. 2006.
[35] K.-H.Tsai, L.-C. Cho, J.-H. Wu, and S.-I. Liu, “3.5-mW W-band frequency divider with wide-locking range in 90-nm CMOS technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb.2008, pp. 466–467.
[36] Y.-T. Chiu, C.-H. Lin, and H.-Y. Chang, “Design and analysis of two modified colpitts VCOs with and without transforme-feedback,” Microwave Integrated Circuits Conference (EuMIC), pp. 430–433, 2011.
[37] T.-N. Luo and Y.-J. E. Chen, “A 0.8-mW 55-GHz dual-injection-locked CMOS frequency divider,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 3, pp. 620–625, Mar. 2008
[38] M.-C. Chen and C.-Y. Wu, “Design and analysis of CMOS subharmonic injection-locked frequency triplers,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 8, pp. 1869–1878, Aug. 2008.
[39] K. Kamogawa, T. Tokumitsu, and M. Aikawa, “Injection-locked oscillator chain: A possible solution to millimeter-wave MMIC synthesizers,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 9, pp.1578–1584, Sep. 1997.
[40] K. Kamogawa, T. Tokumitsu, and I. Toyoda, “A 20-GHz-band subharmonically injection-locked oscillator MMIC with wide-locking-range,” IEEE Microw. Guided Wave Lett., vol. 7, no. 8, pp. 233–235, Aug.1997.
[41] F.-H. Huang, C.-K. Lin, and Y.-J. Chan, “V-band GaAs pHEMT cross-coupled sub-harmonic oscillator,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 8, pp. 473–475, Aug. 2006.
[42] W.-L. Chan, and J.-R. Long., “A 56-65 GHz injection-locked frequency tripler with quadrature output in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2739–2746, Dec. 2008.
[43] S.-W. Tam, E. Socher, A. Wong, Y. Wang, L. D. Vu, and M.-C. F.Chang, “Simultaneous sub-harmonic injection-locked mm-wave frequency generators for multi-band communications in CMOS,” in IEEE RFIC Symp. Dig, Jun. 2008, pp. 131–134.
[44] C.-N. Kuo, and T.-Z. Yan, “A 60-GHz injection-locked frequency tripler with spur suppression,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 10, pp. 560–562, Oct. 2010.
[45] Z. Chen and P. Heydari, “An 85-95.2 GHz transformer-based injection-locked frequency tripler in 65-nm CMOS,” in 2010 IEEE MTT-S Int. Microwave Symp. Dig., May 2010.
[46] F. Maloberti and M. Signorelli, “Quadrature waveform generator with enhanced performances,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 56-57, 1998.
[47] P. Andreani, “A 2-GHz, 17% tuning range quadrature CMOS VCO with high figure-of-merit and 0.6° phase error,” in Proc. IEEE Eur. Solid-State Circuits Conf., Sept. 2002, pp. 815–818.
[48] P. Andreani, A. Bonfanti, L. Romanò, and C. Samori, “Analysis and design of a 1.8-GHz CMOS LC quadrature VCO,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1737–1747, Dec. 2002
[49] John R. Long, “Monolithic transformers for silicon RF IC design”, IEEE J. Solid-State Circuits, vol. 35, no. 9, Sept 2000
[50] C.-K. Hsieh, K.-Y. Kao, Jeffrey Ronald Tseng, and K.-Y. Lin, “A K-Band CMOS low power modified colpitts VCO using transformer-feedback,” IEEE MTT-S Int Microw. Symp. Dig., 2009, pp. 1293-1296.
[51] K. C. Kwok and H. C. Luong, “Ultra-low-voltage high-performance CMOS VCOs using transformer-feedback,” IEEE J. Solid-State Circuits,vol. 40, no. 3, pp. 652–660, Mar. 2005.
[52] T.-H. Huang, and Y.-R. Tseng, “A 1-V 2.2-mW 7-GHz CMOS quadrature VCO using current-reuse and cross-coupled transformer-feedback technology,” IEEE Microwave and Wireless Components Letters, vol. 18, no. 10, pp. 698-700, Oct. 2008.
[53] Y.-C. Chang, Y.-C. Chiu, S.-G. Lin, Y.-Z. Juang, and H.-K. Chiou, “High phase accuracy on-wafer measurement for quadrature voltage-controlled oscillator,” 37th European Microwave Conference (EuMC), Munich, Germany, pp. 340–343. Oct. 2007
[54] S. Hackl, J. Böck, G. Ritzberger, M. Wurzer, and A. L. Scholtz, “A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 135–137, Jan. 2003.
[55] M. Sanduleanu and E. Stikvoort, “Highly linear, varactor-less, 24-GHz IQ oscillator,” in IEEE RFIC Symp. Dig., Jun. 2005, pp. 577–580.
[56] Tormanen, M. Sjoland, H. “A 24-GHz LC-QVCO in 130-nm CMOS using 4-bit switched tuning” Microelectronics, ICM 2008.
[57] H.-D. Zheng, O.-X. Yang, O.-J. Zeng, Li Zhang and Z.-P. Yu, “Design of a 24-GHz wide-tuning-range VCO with optimized switches in resonator”, IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), 2010.
[58] M. Törmänen and H. Sjöland, “A 24-GHz quadrature receiver front-end in 90-nm CMOS,” in Proc. IEEE Asia–Pacific Microw. Conf., Dec. 2009, pp. 1152–1155.
[59] J.-M. Yang, C.-Y. Kim, D.-W. Kim, and S.-C. Hong, “Design of a 24-GHz CMOS VCO with an asymmetric-width transformer,” IEEE Trans. Circuits Syst. II, Exp. Briefs vol. 57, no. 3, Mar 2010
[60] S.-L. Jang, C.-J. Huang, C.-C. Liu, and C.-W. Hsue. “A 0.22 V quadrature VCO in 90-nm CMOS process,” IEEE Microw.Wireless Compon. Lett., vol. 9, no. 9, pp. Sep. 2009.
[61] C.-Y. Kim, J. Yang, D.-W. Kim, and S. Hong, “A K-band quadrature VCO based on asymmetric coupled transmission lines,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2008, pp. 363–366
[62] G.-C. Huang, and B.-S. Kim, “Low phase noise self-switched biasing CMOS LC quadrature VCO”, IEEE Trans. Microw. Theory Tech., vol. 57, no. 9, Feb 2009
[63] S. Zhu, Y. You, D. Heo, J.-H. Kim and B.-S. Kim, “Current-reuse and gate-modulation techniques for sub-1 mW QVCO,” Electronics Letters, vol. 47 , issue: 9, pp.530-531
[64] N. Da Dalt, S. Derksen, P. Greco, C. Sandner, H. Schmid, and K. Strohmayer, “A fully integrated 2.4 GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm digital standard CMOS copper technology,” in Proc. Eur. Solid-State Devices Research Conf., Firenze, Italy, Sep. 2002, pp. 415–418.
[65] T.-N. Luo and Y.-J. E. Chen, “A 0.8-mW 55-GHz dual-injection-locked CMOS frequency divider,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 3, pp. 620-625, Mar. 2008.
[66] J. Hu and B. Otis, “A 3-μW, 400-MHz divide-by-5 injection-locked frequency divider with 56% lock range in 90nm CMOS,” in IEEE RFIC Symp. Dig. Papers, pp. 665–668, 2008.
[67] U. Singh, and M. M. Green, “High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38-GHz,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1658–1661, Aug. 2005.
[68] J. Lee and B. Razavi, “A 40-GHz frequency divider in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 594–601, Apr. 2004.
[69] H. R. Rategh, and T.-H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813–821, Jun. 1999.
[70] Y.-H. Wong, W.-H. Lin, J.-H. Tsai, and T.-W. Huang, “A 50-to-62GHz wide locking-range CMOS injection-locked frequency divider with transformer-feedback,” in IEEE RFIC Symp. Dig. Papers, 2008, pp. 435–438.
[71] M.-W. Li, H.-C. Kuo, T.-H. Huang, and H.-R. Chuang, “60 GHz CMOS divide-by-5 injection-locked frequency divider with an open-stub-loaded floating-source injector,” in IEEE RFIC Dig. Papers, 2011.
[72] Y.-H. Kuo, J.-H. Tsai, H.-Y.Chang, and T.-W. Huang, “Design and analysis of a 77.3% locking-range divide-by-4 frequency divider,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 10, pp. 2477–2485, Oct. 2011.
[73] “Sonnet User’s Guide,” 12th ed. Sonnet Software, Inc., North Syracuse, NY, 2009.
[74] X. Guan, H. Hashemi, and A. Hajimiri, “A fully integrated 24-GHz eight-element phased-array receiver in silicon,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2311–2320, Dec. 2004.
[75] D. Saunders1 et al., “A single-chip 24-GHz SiGe BiCMOS transceiver for FMCW automotive radars”, in IEEE RFIC Dig. Papers, 2009, pp. 459−462.
[76] T.-H. Lin and W. J. Kaiser, “A 900-MHz, 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 424–431, Mar. 2001.
[77] R. R.-B. Sheen, and O. T.-C Chen, “A CMOS PLL-based frequency synthesizer for wireless communication systems at 0.9, 1.8, 1.9 and 2.4-GHz,” 2001 IEEE International Symposium on Circuits and Systems Digest, vol. 4, pp. 722−725, 2000.
[78] Y. Sumi, and et al., “A new PLL frequency synthesizer using multi-programmable divider,” IEEE Transaction on Consumer Electrics, vol. 44, pp. 827−832, Aug. 1998.
[79] G.-Y. Tak, and et al., “A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications,” IEEE J. Solid-State Circuit, vol. 40, pp. 1671−1679, Aug. 2005.
[80] J. M. Ingino and V. R. von Kaenel, “A 4-GHz clock system for a high-performance system-on-a-chip design,” IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1693–1698, Nov. 2001.
[81] S. Steson, R.B. Brown, “A complementary GaAs PLL clock multiplier with wide-bandwidth and low-voltage operation,” 1996 Gallium Arsenide Integrated Circuit (GaAs IC) Symposium Digest, pp. 317–320.
[82] H. R. Rategh, and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813–821, Jun. 1999.
[83] C.-Y. Wu and C.-Y. Yu, “Design and analysis of a millimeter-wave direct injection-locked frequency divider with large frequency locking range,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 8, pp. 1649–1658, Aug. 2007.
[84] M. Soyuer and R. G. Meyer, “Frequency limitations of a conventional phase-frequency detector,” IEEE J. Solid-State Circuits, vol. 25, no. 4, pp. 1019−1022, Aug. 1990.
[85] S. Kim, et al, “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 691−700, May. 1997.
[86] H. Kondoh et al, “A 1.5-V 250-MHz to 3.0-V 622-MHz operation CMOS phase-locked loop with precharge type phase-frequency detector,” IEICE Trans. Electron, vol. E78-C, no. 4, pp. 381−388, Apr, 1995.
[87] B. Razavi, Design of Integration Circuits for Optical Communications, McGraw-Hill, 2003.
[88] H.-H. Chang, J.-W. Lin, C.-Y. Yang, and S.-I. Liu, “A wide-range delay-locked loop with a fixed latency of one clock cycle,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1021−1027, Aug. 2002.
[89] B.-Y. Lin, K.-H. Tsai, and S.-I. Liu, “A 128.24-to-137.00 GHz injection-locked frequency divider in 65-nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 282–283.
[90] J. Jeong and Y. Kwon, “V-Band high-order harmonic injection-locked frequency-divider MMICs with wide bandwidth and low-power dissipation,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 6, pp. 1891–1898, Jun. 2011.
[91] T.-N. Luo, S.-Y. Bai, Y.-J. E. Chen, “A 60-GHz 0.13-μm CMOS divide-by-three frequency divider,” IEEE trans. Microw. Theory Tech., vol.56, no.11, pp. 2409-2415, Nov. 2008.
[92] C.-H. Wang, C.-C. Chen, M.-F. Lei, M.-C. Chuang, and H. Wang, “A 66-72 GHz divide-by-3 injection-locked frequency divider in 0.13-μm CMOS technology,” IEEE ASSCC, pp.344–347, Nov.2007.
[93] Y.-H. Kuo, J.-H. Tsai, W.-H. Chou, and T.-W. Huang, “Admittance-transforming injection-locked frequency divider and low-supply-voltage current mode logic divider,” Microwave Conference Proceedings (APMC), 2010 Asia-Pacific, pp. 782-785.
[94] P.-K Tsai, T.-H. Huang, Y.-H. Pang, “CMOS 40-GHz divide-by-5 injection-locked frequency divider”, Electronics Letters, vol. 46, issue 14, 2010.
[95] W. O. Keese, “An analysis and performance evaluation of a passive filter design technique for charge pump phase-locked loops,” National Semiconductor Application Note, no. 1001, May 1996.
[96] 劉深淵,楊清淵, “鎖相迴路”, 民國97年2月.
[97] Y.-H. Peng, and L.-H. Lu, “A Ku-band frequency synthesizer in 0.18-μm CMOS technology,” IEEE Microw.Wireless Compon. Lett., vol. 17, no. 4, pp. 256–258, Apr. 2007.
[98] Y.-H. Peng, and L.-H. Lu, “A 16-GHz triple-modulus phase-switching prescaler and its application to a 15-GHz frequency synthesizer in 0.18-μm CMOS,” IEEE trans. Microw. Theory Tech., vol. 55, no. 1, pp. 44-51, Nov. 2007.
[99] J. Lee, “High-speed circuit designs for transmitters in broadband data links,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1004–1015, May 2006.
[100] A. W. L. Ng, G. C. T. Leung, K.-C. Kwok, L. L. K. Leung, and H.-C. Luong, “A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-μm CMOS process,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1236–1244, Jun. 2006.
[101] J. Lee, S. Lee, H. Kim, and H. Yu, “A 28.5-to-32 GHz fast settling multichannel PLL synthesizer for 60-GHz WPAN radio,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, pp. 1234-1246, May 2008.
[102] Ng, A. W. L. et al., “A 1-V 24-GHz 17.5-mW PLL in 0.18-μm CMOS,” ISSCC 2005, pp. 158-159, Feb. 2005
[103] J. Lee and H. Wang, "Study of subharmonically injection-locked PLLs," IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1539–1553, May 2009.
[104] P.-K. Tsai, T.-H. Huang, “Integration of current-reused VCO and frequency tripler for 24-GHz low-power phase-locked loop applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 4, Apr. 2012.
[105] J.-H. Liang, Z.-Y. Zhou, J. H., Duncan G. Elliott, “A 6.0-13.5 GHz alias-locked loop frequency synthesizer in 130-nm CMOS,” IEEE Transactions on Circuits and Systems–I: Regular Papers, vol.60, no. 1, Jan. 2013.
[106] Kyujin Oh, Yanping Ding, and Kenneth K. O, “Merged clock data recovery and 24-GHz LO generation circuit for crystalless transcseiver” IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 7, July 2011.
[107] Y.-H. Lin, J.-H. Tsai, Y.-H. Kuo, and T.-W. Huang, “An ultra-low-power 24-GHz phase-lock-loop with low phase-noise VCO embedded in 0.18-μm CMOS process,” Proceedings of the Asia-Pacific Microwave Conference 2011. pp. 1630-1633, Dec. 2011.
[108] M. Huang, C.-H. Yu, J.-H. Tsai, T.-W. Huang, “A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18-μm COMS technology”, Microwave Conference Proceedings (APMC), 2012 Asia-Pacific, pp. 643-645, Dec. 2012.
[109] O. Richard, A. Siligaris, F. Badets, C. Dehos, C. Dufis, P. Busson, P. Vincent, D. Belot, and P. Urard, “A 17.5-to-20.94 GHz and 35-to-41.88 GHz PLL in 65-nm CMOS for wireless HD applications,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 252-253. Feb. 2010,
[110] F. Herzel, S. A. Osmany, K. Schmalz, W. Winkler, J. C. Scheytt, T. Podrebersek, R. Follmann, and H.-V. Heyer, “An integrated 18 GHz fractional-N PLL in SiGe BiCMOS technology for satellite communications,” in Proc. IEEE RFIC Symp., Boston, MA, Jun. 2009, pp. 329–332.
[111] Xiaolei Gai, “A fully integrated low phase noise, fast locking, 31 to 34.9 GHz dual-loop PLL,”Microwave Conference (EuMC), pp. 1209-1212, Oct. 2011.
[112] Xiaolei Gai, “A 35 GHz dual-loop PLL with low phase noise and fast lock for millimeter wave applications,” Microwave Symposium Digest (MTT) 2011, pp.1-4, Jun. 2011.
[113] P.-K. Tsai, C.-Y. Liu, and T.-H. Huang, ‘‘A CMOS voltage-controlled oscillator and frequency tripler for 22−27 GHz local oscillator generation,’’ IEEE Microw. Wirel. Compon. Lett., vol. 21, no. 9, pp. 492−494, Sep. 2011.
[114] B.-Y. Lin, and S.-I. Liu, “A 132.6 GHz phase-locked loop in 65-nm digital CMOS”, IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 58, pp. 617−621, Oct. 2011.
[115] K. Tsutsumi et al., “Low phase noise Ku-band PLL-IC with −104.5 dBc/Hz at 10-kHz offset using SiGe HBT ECL PFD,” in Proc. Asia Pacific Microwave Conf., Dec. 2009, pp. 373–376.
指導教授 張鴻埜(Hong-yeh Chang) 審核日期 2013-3-13
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明