高效率物件切割硬體加速器設計與立體視覺應用

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姓名

黃彥翔(Yen-hsiang Huang) 查詢紙本館藏

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資訊工程學系

論文名稱

高效率物件切割硬體加速器設計與立體視覺應用
(Design and Implementation of a High-Efficiency Segmentation Hardware Accelerator and Application in Stereo Vision)

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摘要(中)

典型的立體視覺原理是基於雙攝影機同步取像和一系列複雜的影像處理，在軟體開發通常需要高效能的處理器以實現複雜演算法，因此使得立體視覺在即時與嵌入式系統的實現開發上受到成本與即時性技術上的限制。本研究藉由MIAT嵌入式硬體設計方法論，設計一個基於SOM神經網路的高效率物件切割硬體加速器，對影像進行色彩切割，並將物件連通標定與基於SAD的立體匹配演算法設計成硬體電路，再以管線化控制器進行平行化架構整合，進而合成全硬體的高速立體視覺系統。其性能可達13.8 Frames/sec，可滿足即時系統需求。其中的高效率物件切割硬體加速器，大幅減少物件切割模組的記憶體存取次數，有效提升物件切割效能。

摘要(英)

A typical stereo vision principle basically consists of two parts. One is the image extracted using two synchronous cameras, and another is a series of complex image processing. However, high-efficacy processors are often required to implement complex algorithms in software development. Thus, stereo vision is difficult to be achieved on the embedded system applications, because of its low-cost and limited resources. In this paper, we designed a high-efficiency segmentation hardware accelerator, based on SOM (Self-Organizing Map) neural network and using Hierarchical Robotic Discrete-Event Modeling, for color segmentation. Then, all the algorithms, connecting component labeling and stereo matching using SAD (Sum of Absolute Difference), were implemented as hardware and integrated with a pipeline controller. Finally, we synthesize a high-speed stereo vision as hardware system. As a result, our system is able to generate images at the speed of up to 13.8 images / sec. This performance makes our system usable in real-time embedded systems. Above all, we reduce the memory access times significantly and raise the performance effectively in high-efficiency segmentation hardware accelerator.

關鍵字(中)

★ SOM神經網路
★ 立體視覺
★ 物件切割
★ FPGA

關鍵字(英)

★ stereo vision
★ segmentation
★ FPGA
★ SOM neural network

論文目次

摘要 I
Abstract II
誌謝 III
目錄 IV
圖目錄 VII
表目錄 X
第一章、緒論 1
1.1 研究背景 1
1.2 研究目標 2
1.3 論文架構 2
第二章、文獻回顧 3
2.1 立體視覺原理 3
2.1.1 針孔攝影機模型 4
2.2 物件切割 6
2.3 立體匹配 8
2.3.1 區域方法 8
2.3.2 全域方法 10
2.4 SOM神經網路硬體設計 11
第三章、嵌入式立體視覺系統設計 13
3.1 雙攝影機取像控制器 14
3.1.1 影像擷取 14
3.1.2 影像記憶體存取控制器 21
3.1.3 影像顯示控制器 22
3.2 影像前處理 23
3.2.1 SOM色彩分群 23
3.2.2 連通物件標定 26
3.2.3 影像記憶體緩衝區 30
3.3 立體匹配 32
3.4 軟體模擬 32
3.4.1 立體視覺演算法模擬 33
3.4.2 深度估測 36
第四章、立體視覺嵌入式硬體設計 38
4.1 硬體合成方法論 38
4.2 雙攝影機取像模組 40
4.3 影像切割模組 43
4.3.1 SOM訓練模組SOM_Train 43
4.3.2 SOM應用模組SOM_Apply 49
4.4 連通物件標定模組 51
4.5 立體匹配模組 54
4.6 管線化控制器與系統整合 55
第五章、系統整合實驗 61
5.1 實驗平台 61
FPGA開發平台 61
CMOS 影像感測器 62
5.2 立體視覺周邊控制模組 66
5.3 SOM物件切割模組 68
5.4 連通物件標定模組 69
5.5 立體匹配模組 70
5.6 系統效能實驗 70
第六章、結論 72
6.1 結論 72
6.2 未來展望 73
參考文獻 74
附錄一 79
SOM神經網路訓練模組 79
SOM神經網路應用模組 80
附錄二 81
連通物件標定模組 81
1 Pass CCP 82
Case 83
Case2 83
Merge 84
General update 85
Merge update 85
附錄三 86
立體匹配模組 86
SAD 87

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指導教授

陳慶瀚(Ching-han Chen)

審核日期

2012-7-4

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