博碩士論文 995301008 詳細資訊




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姓名 陳建忠(Chien-Chung Chen)  查詢紙本館藏   畢業系所 電機工程學系在職專班
論文名稱 應用於生理訊號低功率高解析度之 三角積分調變器
(A Low-Power High-Resolution Sigma-Delta Modulator for Bio-signals)
檔案 [Endnote RIS 格式]    [Bibtex 格式]    至系統瀏覽論文 (2018-8-1以後開放)
摘要(中) 摘要
近年來生醫專用的測量儀器為了日常生活方便使用,需具備微小化可長時間穿戴,高解析度與低功率的類比數位轉換器是必需的。本論文研究應用於生理訊號系統之三角積分類比數位轉換器。因三角積分調變器在類比電路需求較為簡單且寬鬆,相較於其他類型的類比數位轉換器,所以在功率消耗與晶片面積上也可大幅的減少。在此設計一個二階三角積分調變器採用交換式電容電路來實現。

此三角積分調變器使用台積電0.18 um 1P6M CMOS電路技術來實現,在訊號頻寬10 KHz、超取樣率為128倍的情形下,二階輸出SNDR可以達到82.79 dB,具有13.4位元的解析度。在1.8V電壓供給下平均功率消耗為109 µW,有效達到低功率的要求,未來結合後端數位降頻濾波器的實現,將類比與數位電路共同整合,將得以實現混合訊號處理三角積分類比數位轉換器晶片。
關鍵字: 三角積分調變器、切換式電容電路、類比數位轉換器
摘要(英) Abstract
In recent years, biomedical measurement instruments have been used commonly in daily life. In order to achieve micro-size and longtime wearing, high resolution and low power consumption are the necessary factors of analog to digital converter (ADC). The sigma-delta modulator (SDM) ADC for biomedical signals was implemented in this paper. Compared to other types of ADC, the specification of SDM is simple and high tolerance. The SDM ADC also significantly reduces the chip area and power consumption, thus we designed a second-order sigma-delta modulator using switched-capacitor circuits
This circuit was implemented in TSMC 0.18µm 1P6M CMOS process. With the signal bandwidth of 10 KHz and over-sampling ratio of 128, the signal to noise and distortion ratio (SNDR) can achieve 82.79 dB, 13.4 bits resolution, and power consumption is about 109 µW for 1.8 V power supply. The design will combine with the digital decimation filter to achieve mixed signal chip for sigma-delta analog to digital converter used in biomedical signal systems in the future.
Keywords: sigma-delta modulator, switched-capacitor circuits, analog to digital converter (ADC)
關鍵字(中) ★ 三角積分調變器
★ 切換式電容電路
★ 類比數位轉換器
關鍵字(英) ★ sigma-delta modulator
★ switched-capacitor circuits
★ analog to digital converter (ADC)
論文目次 目錄
摘要 I
ABSTRACT II
誌謝 III
目錄 IV
圖目錄 VI
表目錄 X
第一章 緒論 1
1.1研究背景 1
1.2研究動機 3
1.3 論文架構 4
第二章 三角積分調變器原理介紹 5
2.1 奈奎斯特與超取樣類比數位轉換器 5
2.2 量化器 7
2.3 超取樣技術 10
2.4 雜訊移頻技術 11
2.5 一階三角積分調變器 13
2.6 二階三角積分調變器 15
2.7 高階三角積分調變器 17
第三章 三角積分調變器系統規劃與模擬 21
3.1 系統規格制定 21
3.2 電路雜訊與運算放大器非理想效應之考量 23
3.2.1 熱雜訊 24
3.2.2 時脈抖動雜訊 28
3.2.3 運算放大器之有限直流增益 29
3.2.4 運算放大器之有限單位增益頻寬 32
3.2.5 運算放大器之迴轉率 36
3.2.6 比較器之直流電壓偏移 38
3.3整體系統架構非理想效應模擬結果 40
第四章 三角積分調變器電路設計與模擬 43
4.1 交換式電容積分器 43
4.1.1反向積分器 43
4.1.2 非反向積分器 44
4.2 取樣開關 45
4.3 非重疊時脈產生器 49
4.4 運算放大器 50
4.5 共模回授電路 60
4.6 比較器與數位類比轉換器 62
4.7二階交換式電容運算放大器之三角積分調變器設計 64
4.7.1二階交換式電容三角積分調變器 64
4.7.2 電路模擬結果 65
第五章 佈局與量測考量 69
5.1 佈局考量 69
5.2 電路佈局抽取RC模擬結果 70
5.3 量測考量 73
第六章 結論及未來展望 77
6.1 結論 77
6.2 未來展望 77
參考文獻 79
參考文獻 參考文獻
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指導教授 薛木添(Muh-Tian Shiue) 審核日期 2016-7-20
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