博碩士論文 995301015 詳細資訊




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姓名 許志維(Chih-wei Hsu)  查詢紙本館藏   畢業系所 電機工程學系在職專班
論文名稱 應用於 K-band 之倍頻器設計
(Design of Frequency Multipliers for K-band Application)
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摘要(中) 本論文主要以標準台積電(TSMC)SiGe BiCMOS與0.18 um CMOS製程技術,並利用三種不同的電路架構來設計應用於K-band的倍頻器。第一個設計以台積電0.18 um SiGe BiCMOS製程實現一新型的平衡式架構8-24 GHz三倍頻器,此倍頻器於輸出端利用主動式巴倫電路來改善傳統平衡式架構因使用耦合器使得佈局面積過大且限制了調整相位延遲的缺點。第二個設計以台積電0.18 um CMOS製程實現應用主動式轉導提昇共閘極電路技術的12-24 GHz二倍頻器,倍頻器電路以共閘極為主要設計架構,並以一共源極放大器來實現此一轉導提昇級,以提升倍頻器的轉換增益。第三個設計同以台積電0.18 um CMOS製程實現電流再利用電路技術的8-24 GHz三倍頻器,電路中於第二級NMOS電晶體的源極端加入一適當電阻接地以提供而外的電流路徑,如此改善倍頻器在非常小功率輸入條件下的轉換增益,且避免電流的浪費。
摘要(英) This thesis presents the design of K-band frequency multipliers by three circuit topologies in TSMC standard SiGe BiCMOS and 0.18 um CMOS process. In the first design of thesis, we present a new configuration of a balanced 8-24 GHz tripler in TSMC SiGe BiCMOS process. Because of the conventional balanced frequency multipliers usually used couplers and the couplers are too large in dimensions and also limit the phase delay function. So to improve this, the output part of this frequency tripler has been changed by an active balun to instead of the coupler. In the second design of thesis, we present an active Gm-boosted common-gate 12-24 GHz doubler in TSMC 0.18 um CMOS process, the design employs a common-gate configuration and utilizing the common-source configuration as Gm-boosted stage to raise the conversion gain of the doubler. In the third design of thesis, we present an 8-24 GHz tripler with current-reuse technique in TSMC 0.18 um CMOS process, the circuit of tripler places a bypass resistor between common ground and the source node of the second stage NMOS transistor to provide an additional current path and thus improving conversion gain and input power level while saving the waste of current consumption.
關鍵字(中) ★ 倍頻器
★ 主動式巴倫電路
★ 轉導提升
★ 電流再利用式
關鍵字(英) ★ K-band
★ tripler
★ doubler
★ active balun
★ Gm-boosted
★ current reuse
論文目次 摘要 I
Abstract II
致謝 III
目錄 IV
圖目錄 VI
表目錄 IX
第一章 緒論 1
1.1 研究動機與背景 1
1.2 相關研究與發展 1
1.3 論文架構 2
第二章 倍頻器基本原理與設計方法 3
2.1 簡介 3
2.2 倍頻器各重要參數介紹說明 3
2.3 倍頻器的組成考量與架構簡介 5
2.3.1 被動式倍頻器(Passive Frequency Multipliers) 5
2.3.2 主動式倍頻器(Active Frequency Multipliers) 9
2.4 討論 11
第三章 8-24 GHz主動平衡式三倍頻器之設計 13
3.1 前言 13
3.2 研究動機與方法 13
3.3 電路架構與設計之模擬分析 15
3.4 模擬與量測結果 19
3.5 結果與討論 26
3.6 結論 30
第四章 12-24 GHz主動式轉導提昇共閘極倍頻器電路設計 31
4.1 前言 31
4.2 研究動機與方法 31
4.3 電路設計與架構分析 32
4.4 模擬與量測結果 34
4.5 結果與討論 42
4.6 結論 43
第五章 8-24 GHz電流再利用式三倍頻器之設計 44
5.1 前言 44
5.2 研究動機與方法 44
5.3 電路設計與架構分析 45
5.4 模擬與量測結果 49
5.5 結果與討論 56
5.6 結論 56
第六章 結論 58
參考文獻 60
參考文獻 參考文獻
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指導教授 辛裕明(Yue-ming Hsin) 審核日期 2014-7-17
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