博碩士論文 995401020 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:13 、訪客IP:3.238.184.78
姓名 簡冠修(Kuan-Hsiu Chien)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於無線感測網路之K-頻段開關鍵控發射機與接收機電路之研製
(Study on K-band On-Off Keying Transmitter/Receiver for Wireless Sensor Network Applications)
相關論文
★ 應用於筆記型電腦數位電視單極天線之研製★ 應用於數位機上盒與纜線數據機之電纜多媒體傳輸標準多工濾波器
★ 印刷共面波導饋入式多頻帶與超寬頻天線設計★ 微波存取全球互通頻段前向匯入式功率放大器與高效率Class F類功率放大器暨壓控振盪器電路之研製
★ 應用於矽基功率放大器與混頻器之傳輸線型變壓器研究★ 應用於V-頻段射頻收發機前端電路之低功耗源極注入式混頻器之研製
★ 應用積體電路上方後製程與整合被動元件於互補式金氧半導體製程之系統封裝研究★ 應用fT-倍頻電路架構於毫米波壓控振盪器與注入鎖定除頻器之研製
★ 應用傳輸線型變壓器於X/K–Ka/V頻段全積體整合之寬頻互補式金氧半導體功率放大器研製★ 應用於K / V 頻段低功耗混頻器之研製
★ 應用於K/V頻段之低功耗CMOS低雜訊放大器之研究★ 應用於5-GHz CMOS射頻前端電路之低電壓自偏壓式混頻器與高線性化功率放大器之研製
★ 應用於 K 頻段射頻接收機之寬頻低功耗 CMOS 低雜訊放大器之研製★ 應用磁耦合變壓器於K頻段之低功耗互補式金氧半導體壓控振盪器研製
★ 應用於K頻段之單向化全積體整合功率放大器與應用於V頻段之寬頻功率放大器研製★ 應用於C/X頻段全積體整合之互補式金氧半導體寬頻低功耗降頻器與寬頻功率混頻器之研製
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 ( 永不開放)
摘要(中) 本篇論文設計應用於無線感測網路之K-頻段開關鍵控發射機與接收機電路,論文包含使用台積電CMOS 0.18 μm製程研製的低消耗功率、寬頻鎖定之達靈頓架構除三與除二注入鎖定除頻器。以及使用台積電CMOS 90 nm製程研製的寬頻低功耗、低雜訊指數之低雜訊放大器,以及K-頻段開關鍵控發射機與接收機。整體電路以低消耗功率為設計目標。
本篇論文第二章提出低消耗功率、寬鎖定寬頻之達靈頓架構除三與除二注入鎖定除頻器。除三之注入鎖定除頻器以達靈頓架構提升電路轉導能力,進而將低消耗功率以及利用差動注入器方式以增強注入電流,達到寬的注入頻寬特性。而除二之注入鎖定除頻器則使用達靈頓架構結合LC共振技術,將更為提升電路轉導能力,更加降低整體電路消耗功率。整體電路性能方面,除三之注入鎖定除頻器具有24.71 GHz至28 GHz操作頻率頻寬,在位移頻率為1 MHz時,其鎖定相位雜訊為-140.35 dBc/Hz;本電路之供應電壓為1.45 V,消耗功率為5.13 mW,整體晶片尺寸為0.77×0.79 mm2。除二之注入鎖定除頻器具有20.5 GHz至22.9 GHz鎖定頻寬,在位移頻率為1 MHz時,其鎖定相位雜訊為-138.3 dBc/Hz;本電路之供應電壓為1.2 V時,消耗功率為1.73 mW,整體晶片尺寸為0.8×0.75 mm2。
第三章介紹一顆寬頻低功耗且低雜訊之低雜訊放大器,使用電流再利用技術達到低消耗功率與高增益的特性,輸入匹配則採用正回授之變壓器技術,可以得最佳雜訊與增益且寬頻的響應,並同時達到縮小晶片面積;另外,為了改善線性度問題採用一顆補償gm3放大器產生一個負的gm3與電流再利用的gm3相消,藉以提升電路的IIP3。在供應電壓為0.8 V,消耗功率為4.76 mW時,電路得到最高增益與最低雜訊分別為11.98 dB與2.83 dB,P1-dB與IIP3分別為-12 dBm與-3.35 dBm,整體FOM1,增益,雜訊指數,頻寬,OIP3.,操作頻率與dc消耗功率提升至79.44與近年來文獻比較有最好的表現,整體晶片尺寸為0.84×0.6 mm2。
第四章介紹一顆應用於無線感測網路之K-頻段開關鍵控發射機電路,為了實現低消耗功率且具寬頻之發射機電路,在設計上使用一個寬頻的12 GHz之壓控振盪器電路,此振盪器使用了新式的負電阻以降低交錯耦合負阻的寄生電容以達到寬頻之設計,再使用操作在Class B的倍頻器以達到最佳功率轉換效率。而功率放大器則採用Class AB之疊接組態來實現,並且在共源級的閘極端輸入調變訊號,以達到較高的隔離度與快速的資料比之發射機性能。本電路之量測結果如下,可調頻率範圍為19 GHz至23.1 GHz,在位移頻率為1 MHz時相位雜訊為-96.17 dBc/Hz,最大輸出功率為2.91 dBm,消耗功率為22.3 mW,最高傳輸資料率為500 Mbps,換算之能量效率為44 pJ/bit,整體晶片面積為0.6 × 0.92 mm2。
第五章介紹一顆應用於無線感測網路之K-頻段開關鍵控接收機電路,此接收機由低雜訊放大器、封包檢測器及中頻可調增益放大器結合補償直流位移器組成。低雜訊放大器採用兩級共源級放大器並使用正迴授放大器,以達節省面積與低消耗功率寬頻設計:於負載為200 Ω時,整體3-dB頻寬為17 GHz至23.4 GHz,最大增益為20.47 dB。為了降低消耗功率與提高解調之靈敏度,採用單轉雙之封包檢測器並偏壓接近臨界電壓。中頻可調增益則採用三級Cherry-Hooper放大器實現,此架構為一級共源級放大器提供高增益。第二級採用並並回授以得到寬的頻寬,整體可調增益範圍為62.6 dB,而3-dB頻寬為100 kHz至1.4 GHz。由於差動輸出具有直流位移問題,此設計加入一組一階低通濾波器與轉導放大器補償直流位準偏移。整體接收機的性能,在供應電壓為1 V,資料率為600 Mbps時,接收機之消耗功率與平均消耗功率分別為9.52 mW與15.86 nW,最低靈敏度為-47.6 dBm,整體晶片面積為1×0.81 mm2。
摘要(英) This study develops a K-band On-Off keying (OOK) transmitter and receiver for wireless sensor network (WSN) applications. A divide-by-3 and a divide-by-2 injection locked frequency divider are implemented by Darlington topology to achieve low power and wide locking range in tsmcTM CMOS 0.18 μm process. This study also develops K-band OOK transmitter and receiver that feature the performance of wideband, low power, low noise figure and high data rate in tsmcTM CMOS 90 μm technology.
In Chapter 2, the divide-by-two and divide-by-three injection-locked frequency dividers (ILFDs) using Darlington cell in tsmcTM 0.18 µm CMOS process. The Darlington cell has higher transconductance than traditional cross-coupled common source cell for free-running oscillator that reduces the power consumption of ILFDs. Besides, an LC resonance technique is used in the proposed divide-by-two ILFD to achieve lower power consumption and wide locking range. The measured locking range of the proposed divide-by-two ILFD is from 20.5 to 22.9 GHz. And the measured operation range of the divide-by-three ILFD is from 24.71 to 28 GHz. The measured phase noises of two dividers under locked condition are -138.3 and -140.35 dBc/Hz at an offset of 1-MHz when the input referred signals have phase noises of -132.54 and -131.5 dBc/Hz, respectively. The core power consumptions are 1.73 and 5.13 mW with the supply voltages of 1.2 and 1.45 V, and the chip sizes are 0.8 × 0.75 mm2 and 0.77 × 0.79 mm2, respectively.
Chapter 3 presents a low-power and wideband CMOS low noise amplifier (LNA) with current-reused and gate-source transformer feedback techniques to obtain simultaneous noise and impedance matching from 14.7 to 26.7 GHz. The LNA also adopts an auxiliary amplifier to cancel the output third-order transconductance for linearity improvement. The LNA is fabricated in tsmcTM 90 nm CMOS technology and achieves a peak gain |S21| of 11.98 dB and a minimum noise figure (NF) of 2.8 dB. The measured input third-intercept point (IIP3) is -3.35 dBm at 17 GHz under dc power of 4.76 mW from a 0.8 V supply voltage. The overall figure-of-merit (FoM1) regarding gain, noise figure, bandwidth, OIP3, operation frequency, and dc power is up to 79.44 which is the highest one among the recently published works. The chip size of the fabricated LNA is 0.84 × 0.6 mm2.
Chapter 4 proposes a high energy-efficiency K-band OOK transmitter in tsmcTM 90 nm CMOS technology. The transmitter consists of a wideband voltage control oscillator (VCO), a frequency doubler and a switch-type power amplifier (PA) with a chip area of 0.6 × 0.92 mm2. The VCO adopts a parasitic capacitance reduction technique to enhance the tuning range to 20.5%. The designed transmitter achieves an output power of 3 dBm with a 500 Mbps data rate from 19 to 23.1 GHz at 22.3 mW power consumption. The correspondent energy-efficiency is 44 pJ/bit.
Chapter 5 proposes an OOK receiver which is realized in tsmcTM 90 nm CMOS process. The OOK receiver consists of a two-stage wideband LNA, a single-to-differential envelop detector with RC low pass filter and a 62.6 dB three-stage variable gain amplifier (VGA) with DC offset compensation circuit. The OOK receiver achieved a sensitivity of -47.6 dBm at 600 Mbps data rate under a pseudo random binary sequence (PRBS) 29-1 pattern. The receiver consumes a low power of a 9.5 mW which minimum average power is only 15.86 nW at the input power of -47.6 dBm. The chip area including the test pads is 1 × 0.81 mm2.
關鍵字(中) ★ 注入鎖定除頻器
★ 低雜訊放大器
★ 開關鍵控發射機
★ 開關鍵控接收機
關鍵字(英) ★ injection locked frequency divider
★ low noise amplifier
★ OOK transmitter
★ OOK receiver
論文目次 中文摘要 I
Abstract III
誌謝 V
圖目錄 List of Figures X
表目錄 List of Tables XV
Chapter 1 Introduction 1
1. 1 Background and Motivation 1
1. 2 Literature Survey 5
1. 3 Dissertation Organization 7
Chapter 2 Design of K-band Divide-by-Two and Divide-by-Three Injection-Locked Frequency Divider with Darlington Topology 9
2. 1 Circuit Topology 10
2. 2 Analysis of Locking Range for ILFD 11
2. 2. 1 Quality Factor of Small-Signal Model 12
2. 2. 2 Analysis of the Injection Current of the Injector 13
2. 2. 3 Analysis of the Transconductance and Current of the Oscillator 16
2. 3 Circuit Design 21
2. 3. 1 Darlington Cell for Divide-by-Three ILFD 22
2. 3. 2 Darlington Cell with LC Resonance for Divide-by-Two ILFD 24
2. 4 Measurement Results 27
2. 5 Summary 35
Chapter 3 A Full K-Band Low-Power CMOS LNA with Current-Reused and Transformer-Feedback Techniques 37
3. 1 Schematic of the Ultra-Low Power and Wideband LNA 37
3. 2 Design and Analysis of the Proposed LNA 39
3. 2. 1 Input Impedance and Input Matching 39
3. 2. 2 Noise Figure 43
3. 2. 3 Voltage Gain 45
3. 2. 4 Output Swing and Linearity 47
3. 3 Circuit Design 50
3. 4 Measurement Results 54
3. 5 Summary 58
Chapter 4 High Energy-Efficiency and High Data Rate K-band OOK Transmitter for Wireless Sensor Networks 59
4. 1. Function Block of the Proposed K-band OOK Transmitter 59
4. 2. Design of the Proposed K-band OOK Transmitter 61
4. 2. 1 Wideband VCO 61
4. 2. 2 Frequency Doubler 65
4. 2. 3 Switch-Type PA 66
4. 3. Measurement Results 67
4. 4. Summary 72
Chapter 5 High Sensitivity, High Data Rate and Low Power OOK Receiver for Wireless Sensor Networks 74
5. 1. Function Block of the Proposed K-band OOK Receiver 74
5. 2. Design of the Proposed K-band OOK Receiver 77
5. 2. 1 LNA 77
5. 2. 2 Signal-to-Differential Envelop Detector 80
5. 2. 3 Variable Gain Amplifier with DC Offset Compensation Circuit 83
5. 3. Measurement Results 87
5. 4. Summary 90
Chapter 6 Conclusion and Future Works 91
Bibliography 94
Publications 104
參考文獻 [1] J. Li, C. D., J. Zhang, “Power-aware routing protocols in AD HOC wireless networks,” IEEE Wireless Communications, vol. 12, no. 6, pp. 69-81, Dec. 2005.
[2] M. A. M. Vieira, D. C. da Silva Junio, C. N. Coelho. Jr. and J. M. da Mata, “Survey on wireless sensor network devices,” in IEEE Emerging Technologies and Factory Automation Conference, 2003, pp. 537-544.
[3] W. Wu, M. A. T. Sanduleanu, X. Li and J. R. Long, “17 GHz RF front-ends for low-power wireless sensor networks,” IEEE J. Solid-State Circuits, vol. 43, no. 9, pp.1909-1919, Sep. 2008.
[4] C. J. Hwang, I. McGregor, R. Oxland, G. Whyte, I. G. Thayne and K. Elgaid, “An ultra-low power OOK RF transceiver for wireless sensor networks,” in European Microwave Conf., Sep. 2009, pp. 1323- 1326.
[5] C. W. Byeon, C. H. Yoon and C. S. Park, “A 67-mW 10.7-Gb/s 60-GHz OOK CMOS transceiver for short-range wireless communications,” IEEE Trans. Microwave Theory Tech., vol. 61, no. 9, pp. 3391-3401, Sep. 2009.
[6] P. Upadhyaya, M. Rajashekharaiah, D. Heo, D. M. Rector, Y. J. E. Chen, “Low power and low phase noise 5.7 GHz LC VCO in OOK transmitter for neurosensory application,” in IEEE MTT-S International Microwave Symp. Digest, 2005, pp. 1539–1542.
[7] K. Kim, J. Choi, M. Seo and S. Nam, “500 MHz OOK transmitter with 22 pJ/bit, 38.4% efficiency using RF current combining,” IEEE Microw. Wireless Compo. Lett., vol. 24, no. 6, pp. 424-426, Jun. 2014.
[8] P. Favre, N. Joehl, A. Vouilloz, P. Deval, C. Dehollain and M. J. Declercq, “A 2-V 600- A 1-GHz BiCMOS super-regenerative receiver for ISM applications,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2186-2196, Dec. 1998.
[9] H.-G. Park, J. Lee, J.-A Jang, J.-H. Jang, D.-S. Lee, H.-J. Kim, S.-J. Kim, S.-G. Lee and K.-Y. Lee, “An ultra-low-power super regeneration oscillator-based transceiver with 177- μW leakage-compensated PLL and automatic quench waveform generator,” IEEE Trans. Microwave Theory Tech., vol. 61, no. 9, pp. 3381-3390, Sep. 2013.
[10] K. Kang, F. Lin, D.-D. Pham, J. Brinkhoff, C.-H. Heng, Y. X. Guo and X. Yuan, “A 60-GHz OOK receiver with an on-chip antenna in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1720-1731, Sep. 2010.
[11] X. Huang, P. Harpe, G. Dolmans, H. de Groot and J. R. Long, “A 780–950 MHz, 64–146 μW power-scalable synchronized-switching OOK receiver for wireless event-driven applications,” IEEE J. Solid-State Circuits, vol. 49, no. 5, pp. 1135-1147, May 2014.
[12] Y. Mo, E. Skafidas, R. Evans and I. Mareels, “A 40 GHz power efficient static CML frequency divider in 0.13-μm CMOS technology for high speed millimeter-wave wireless systems,” in IEEE International Conference Circuits and Systems for Communications, 2008, pp. 812-815.
[13] C. Zhou, L. Zhang, Y. Wang, Z. Yu and H. Qian, “Injection-locking-based power and speed optimization of CML dividers,” IEEE Tran. Circuits and Systems—II: Express Briefs, vol. 58, no. 9, pp. 565-569, Sep. 2011.
[14] J.-O. Plouchart, J. Kim, V. Karam, R. Trzcinski and J. Gross, “Performance variations of a 66GHz static CML divider in 90nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp. 2142-2151.
[15] U. Singh and M. M. Green, “High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1658-1661, Aug. 2005.
[16] X. Yi, C. C. Boon, M. A. Do, K. S. Yeo and W. M. Lim, “Design of ring-oscillator-based injection-locked frequency dividers with single-phase inputs,” IEEE Microw. Wiless Compon. Lett., vol. 21, no. 10, pp. 559-561, Oct. 2011.
[17] S.-L. Jang, Y.-H. Chuang, S.-H. Lee and J.-J. Chao, “Circuit techniques for CMOS divide-by-four frequency divider,” IEEE Microw. Wiless Compon. Lett., vol. 17, no. 3, pp. 217-219, Mar. 2007.
[18] R.-F. Ye, T.-S. Horng and J.-M. Wu, “Low power FSK receiver using an oscillator-based injection-locked frequency divider,” IEEE Microw. Wiless Compon. Lett., vol. 24, no. 2, pp. 114-116, Feb. 2014.
[19] Y.-S Lin, C.-H. Wu, C.-C. Huang, C.-L. Lu and Y.-H. Wang, “Ultra-wide locking range regenerative frequency dividers with quadrature-injection current-mode-logic loop divider,” IEEE Microw. Wiless Compon. Lett., vol. 24, no. 3, pp. 179-181, Mar. 2014.
[20] Y.-S. Lin, C.-H. Wu, C.-L. Lu and Y.-H. Wang, “A divide-by-four transformer-coupled regenerative frequency divider with quadrature outputs,” IEEE Microw. Wiless Compon. Lett., vol. 24, no. 4, pp. 260-262, Apr. 2014.
[21] C.-A. Yu, T.-N. Luo and Y.-J. E. Chen, “A V-band divide-by-four frequency divider with wide locking range and quadrature outputs,” IEEE Microw. Wiless Compon. Lett., vol. 22, no. 2, pp. 260-262, Feb. 2012.
[22] Y.-H. Kuo, J.-H. Tsai, T.-W. Huang and H. Wang, “Design and analysis of digital-assisted bandwidth-enhanced miller divider in 0.18- μm CMOS process,” IEEE Trans, Microw. Theory Techn., vol. 60, no. 12, pp. 3769-3777, Dec. 2012.
[23] W.-S. Chang, K.-W. Tan and S. S. H. Hsu, “A 56.5–72.2 GHz transformer-injection miller frequency divider in 0.13μm CMOS,” IEEE Microw. Wiless Compon. Lett., vol. 20, no. 7, pp. 393-395, Jul. 2010.
[24] T.-N. Luo, S.-Y. Bai and Y.-J. Emery Chen, “A 60-GHz 0.13-μm CMOS divide-by-three frequency divider,” IEEE Trans, Microw. Theory Techn., vol. 56, no. 11, pp. 2409-2415, Nov. 2008.
[25] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sep. 2004.
[26] Y.-L. Yeh and H.-Y. Chang, “Design and analysis of a W-band divide-by-three injection-locked frequency divider using second harmonic enhancement technique,” IEEE Trans, Microw. Theory Techn., vol. 60, no. 6, pp. 1617-1625, Jun. 2012.
[27] C.-Y. Wu and C.-Y. Yu, “Design and analysis of a millimeter-wave direct injection-locked frequency divider with large frequency locking range,” IEEE Trans, Microw. Theory Techn., vol. 55, no. 8, pp. 1649-1658, Aug. 2007.
[28] K.-C. Lin, H.-K. Chiou, K.-H. Chien, T.-Y. Yang, P.-C. Wu, C.-L. Ko and Y.-Z. Juang, “A 4.2-mW 6-dB gain 5–65-GHz gate-pumped down-conversion mixer using Darlington cell for 60-GHz CMOS Receiver,” IEEE Trans, Microw. Theory Techn., vol. 61, no. 4, pp. 1516-1522, Apr. 2013.
[29] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717-724, May 1999.
[30] S.-L. Jang, C.-W. Chang, W.-C. Cheng, C.-F. Lee and M.-H. Juang, “Low-power divide-by-3 injection-locked frequency dividers implemented with injection transformers,” Electron. Lett., vol. 45, no. 5, pp. 240-241, Feb. 2009.
[31] S. Rong and H. C. Luong, “A 1V 1.7mW 25GHz transformer-feedback divide-by-3 frequency divider with quadrature outputs,” IEEE Asian Solid-State Circuits Tech., pp. 328-331, Nov. 2007.
[32] S. Seo, H. Seo, S. Jeon and J.-S. Rieh, “A 20–30 GHz divide-by-3 ring-oscillator-based injection locked frequency divider with a wide locking range,” Microwave and Optical Technology Letters, vol. 53, no. 4, pp. 839-841, Apr. 2011.
[33] M.-W. Li, P.-C. Wang, T.-H. Huang, “Low-voltage, wide-locking-range, millimeter-wave divide-by-5 injection-locked frequency dividers,” IEEE Trans, Microw. Theory Techn., vol. 60, no. 3, pp. 679-685, Mar. 2012.
[34] S.-L. Jang, R.-K. Yang, C.-W. Chang and M.-H. Juang, “Multi-modulus LC injection-locked frequency dividers using single-ended injection,” IEEE Microw. Wiless Compon. Lett., vol. 19, no. 5, pp. 311-313, May 2009.
[35] Y.-T. Chen, M.-W. Li, H.-C. Kuo, T.-H. Huang and H.-R. Chuang, “Low-voltage K-band divide-by-3 injection-locked frequency divider with floating-source differential injector,” IEEE Trans, Microw. Theory Techn., vol. 60, no. 1, pp. 60-67, Jan. 2012.
[36] K.-H. Tsai, L.-C. Cho, J.-H.Wu and S.-I. Liu, “3.5 mW W-band frequency divider with wide locking range in 90 nm CMOS technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 466–467.
[37] T.-N. Luo and Y.-J. E. Chen, “A 0.8-mW 55-GHz dual-injection-locked CMOS frequency divider,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 3, pp. 620–625, Mar. 2008.
[38] Y.-H. Kuo, J.-H. Tsai, H.-Y. Chang and T.-W. Huang, “Design and analysis of a 77.3% locking-range divide-by-4 frequency divider,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 10, pp. 2477–2485, Oct. 2011.
[39] B.-J. Huang, K.-Y. Lin and H. Wang, “Millimeter-wave low power and miniature CMOS multicascode low-noise amplifiers with noise reduction topology,” IEEE Trans, Microw. Theory Techn., vol. 57, no. 12, pp. 3049-3059, Dec. 2009.
[40] H.-C. Yeh, Z.-Y. Liao and H. Wang, “Analysis and design of millimeter-wave low-power CMOS LNA with transformer-multicascode topology,” IEEE Trans, Microw. Theory Techn., vol. 59, no. 12, pp. 3441-3454, Dec. 2011.
[41] H.-C. Yeh, C.-C. Chiong, S. Aloui and H. Wang, “Analysis and design of millimeter-wave low-voltage CMOS cascode LNA with magnetic coupled technique,” IEEE Trans, Microw. Theory Techn., vol. 60, no. 12, pp. 4066-4079, Dec. 2012.
[42] K.-J. Sun, Z.-M. Tsai, K.-Y. Lin and H. Wang, “A 10.8-GHz CMOS low-noise amplifier using parallel-resonant inductor,” in IEEE MTT-S International Microw. Symposium Digest, 2007, pp. 1795-1798.
[43] H.-C. Yeh and H. Wang, “A miniature Q-band CMOS LNA with quadruple-cascode topology,” in IEEE MTT-S International Microw. Symposium Digest, 2011, pp. 1-4.
[44] R.-M. Weng, C.-Y. Liu and P.-C. Lin, “A low-power full-band low-noise amplifier for ultra-wideband receivers,” IEEE Trans, Microw. Theory Techn., vol. 58, no. 8, pp. 2077-2083, Aug. 2010.
[45] C.-P. Chang, J.-H. Chen and Y.-H. Wang, “A fully integrated 5 GHz low-voltage LNA using forward body bias technology,” IEEE Microw. Wiless Compon. Lett., vol. 19, no. 3, pp. 176-178, Mar. 2009.
[46] H.-H. Hsieh and L.-H. Lu, “Design of ultra-low-voltage RF frontends with complementary current-reused architectures,” IEEE Trans, Microw. Theory Techn., vol. 55, no. 7, pp. 1445-1458, Jul. 2007.
[47] D.-H. Shin, J. Park and C.-P. Yue, “A low-power, 3–5-GHz CMOS UWB LNA using transformer matching technique,” in IEEE Asian Solid-State Circuits Conference, 2007, pp. 95-98.
[48] T.-K. Nguyen, C.-H. Kim, G.-J.Ihm, M.-S. Yang and S.-G. Lee, “CMOS low noise amplifier design optimization techniques,” IEEE Trans, Microw. Theory Techn., vol. 52, no. 5, pp. 1433-1442, May 2004.
[49] J.-R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1368-1382, Sep. 2000.
[50] G. Gonzalez, “Microwave Transistor Amplifiers: Analysis and Design,” 2nd ed. Upper Saddle River. Englewood Cliffs, NJ, USA: Prentice-Hall, 1997.
[51] B. Razavi, “Design of Analog CMOS Integrated Circuits,” NewYork, NY, USA: McGraw-Hill, 2001.
[52] V. Aparin and L.-E. Larson, “Modified derivative superposition method for linearizing FET low-noise amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 53, no. 2, pp. 571–581, Feb. 2005.
[53] T. Joo et al, “A WLAN RF CMOS PA with large-signal MGTR method,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 3, pp. 1272–1279, Mar. 2013.
[54] T.-W. Kim et al, “Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 223–229, Jan. 2004.
[55] T. Yao et al, “Algorithmic design of CMOS LNAs and PAs for 60-GHz radio,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1044–1057, May 2007.
[56] T. O. Dickson et al, “The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1830–1845, Aug. 2006.
[57] S.-C. Shin, M.-D Tsai, R.-C. Liu, K.-Y. Lin and H. Wang, “A 24-GHz 3.9-dB NF low-noise amplifier using 0.18 μm CMOS technology,” IEEE Microw. Wiless Compon. Lett., vol. 15, no. 7, pp. 448-450, Jul. 2005.
[58] Y.-L. Wei, Shawn S. H. Hsu and J.-D. Jin, “A low-power low-noise amplifier for K-band applications,” IEEE Microw. Wiless Compon. Lett., vol. 19, no. 2, pp. 116-118, Feb. 2005.
[59] M.-H. Tsai, Shawn S. H. Hsu, F.-L. Hsueh, C.-P. Jou, T.-J. Yeh, J.-D. Jin and H.-H. Hsie, “A 24-GHz low-noise amplifier co-designed with ESD protection using junction varactors in 65-nm RF CMOS,” in IEEE MTT-S International Microw. Symposium Digest, 2011, pp. 1-4.
[60] H.-Y. Chang, C.-H. Lin, Y.-C. Liu, Y.-L. Yeh, K. Chen and S.-H. Wu, “65-nm CMOS dual-gate device for Ka-band broadband low-noise amplifier and high-accuracy quadrature voltage-controlled oscillator,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 6, pp. 2402–2413, Jun. 2005.
[61] F. Inanlou, C.-T. Coen and J.-D. Cressler, “A 1.0 V, 10–22 GHz, 4 mW LNA utilizing weakly saturated SiGe HBTs for single-chip, low-power, remote sensing applications,” IEEE Microw. Wiless Compon. Lett., vol. 24, no. 12, pp. 890-892, Dec. 2014.
[62] T. Kanar and G.-M. Rebeiz, “X- and K-band SiGe HBT LNAs with 1.2- and 2.2-dB mean noise figures,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 10, pp. 2381–2389, Oct. 2014.
[63] E.-N. Mohamed, S.-S. Edgar and E. Kamran, “A millimeter-wave (23–32 GHz) wideband BiCMOS low-noise amplifier,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 289–299, Feb. 2010.
[64] M. Chen and J. Lin, “A 0.1–20 GHz low-power self-biased resistive-feedback LNA in 90 nm digital CMOS,” IEEE Microw. Wiless Compon. Lett., vol. 19, no. 5, pp. 323-325, May 2009.
[65] E. Adabi, B. Heydari, M. Bohsali and A.-M. Niknejad, “30 GHz CMOS low noise amplifier,” in IEEE Radio Frequency Integrated Circuits Symposium, 2007, pp. 625-628.
[66] P. K. Tsai, C. Y. Liu and T. H. Huang, “A CMOS voltage controlled oscillator and frequency tripler for 22 – 27 GHz local oscillator generation” IEEE Microw. Wiless Compon. Lett., vol. 21, no. 9, pp. 492-494, Sep. 2011.
[67] H.-Yeh Chang, M.-F. Lei, C.-S. Lin, Y.-H. Cho, Z.-M. Tsai and H. Wang, “A 46-GHz direct wide modulation bandwidth ASK modulator in 0.13-μm CMOS technology,” IEEE Microw. Wiless Compon. Lett., vol. 17, no. 9, pp. 691-693, Sep. 2007.
[68] P. Favre, N. Joehl, A. Vouilloz, P. Deval, C. Dehollain and M.-J. Declercq, “A 2-V 600-μA 1-GHz BiCMOS super-regenerative receiver for ISM applications,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2186-2196, Dec. 1998.
[69] H.-G. Park, J. Lee, J.-A Jang, J.-H. Jang, D.-S. Lee, H.-J. Kim, S.-J. Kim, S.-G. Lee and K.-Y. Lee, “An ultra-low-power super regeneration oscillator-based transceiver with 177-μW leakage-compensated PLL and automatic quench waveform generator,” IEEE Trans, Microw. Theory Techn., vol. 61, no. 9, pp. 3381-3390, Sep. 2013.
[70] Y. Wang, B. Afshar, LuYe, V.-C. Gaudet and A.-M. Niknejad, “Design of a low power, inductorless wideband variable-gain amplifier for high-speed receiver systems,” IEEE Tran. Circuits and Systems—I: Express Briefs, vol. 59, no. 4, pp. 696-707, Apr. 2012.
[71] S.-L. Jang, C.-F. Lee and W.-H. Yeh, “A divide-by-3 injection locked frequency divider with single-ended input,” IEEE Microw. Wiless Compon. Lett., vol. 18, no. 2, pp. 142-144, Feb. 2008.
[72] H.-R. Rategh, H. Samavati and T.-H. Lee, “A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 780-787, May 2000.
指導教授 邱煥凱(Hwann-Kaeo Chiou) 審核日期 2016-1-14
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明