Ka與V頻段低雜訊與寬頻放大器之研製

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姓名

林凱筠(Kai-Yun Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

Ka與V頻段低雜訊與寬頻放大器之研製
(Implementation of Ka-Band and V-Band Low Noise Amplifier and Broadband Amplifier)

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摘要(中)

本論文主要研究內容為Ka頻段與V頻段射頻毫米波頻段前端電路設計。所設計的晶片皆利用WIN 0.15 um pHEMT與TSMC 0.18 um CMOS製程研製。本論文所設計之晶片包含了低雜訊放大器以及分佈式放大器。低雜訊放大器使用三級串接式架構來實現，前兩級針對低雜訊做匹配，最後一級則是以取得高增益為目標。傳輸線部分除了常見的微帶線之外，亦利用了有限接地共平面波導的形式。有限接地共平面波導因為具有容易製作、方便與同平面元件連接以及減少輻射損耗等優點，適合用來設計微波及毫米波電路中之走線。本論文亦針對有限接地共平面波導的接地平面寬度作模擬，以期得到最佳之電路效能。至於分佈式大器部分則是採用三級串接式分佈式放大器架構，針對高增益做匹配，達到在單位面積內可得到最大之增益。
所設計之晶片其量測與模擬結果如下，V頻段低雜訊放大器在50 GHz的增益為20.7 dB，輸入1-dB壓縮點為-15 dBm，模擬之雜訊指數在60 GHz為4.2 dB；V頻段共平面波導低雜訊放大器在50 GHz的增益為22.17 dB，輸入1-dB壓縮點為-18 dBm，模擬雜訊指數在60 GHz為5.2 dB；20-35 GHz串接分佈式寬頻放大器在頻率範圍內增益大於5 dB，在20 GHz時，增益為12.1 dB，輸入1-dB壓縮點功率在20 GHz為-10 dBm、28 GHz為-7 dBm；26-65 GHz串接分佈式寬頻放大器在頻寬達39 GHz內，增益為大於16.5 dB，輸入1-dB壓縮點功率為大於-15 dBm。

摘要(英)

The thesis focuses on the millimeter wave receiver front-end circuit designs, which include the low noise amplifiers in V band. The circuits are fabricated by WIN 0.15 um pHEMT and TSMC 0.18 um CMOS process.
Chips designed in this thesis include the low noise amplifier and distributed amplifier. The low noise amplifier is implemented by cascading three stages, the first two stage is designed for low noise while the last stage is matched for high gain. Except microstrip line, the transmission line also presents by finite-width ground coplanar waveguide. Finite-width ground coplanar waveguide has the benefits with simplifying the fabrication, facilitating easy shunt as well as series surface mounting of devices, and reducing radiation loss and suits for designing the route in microwave and millimeter wave circuit. The width of the ground line of the finite-width ground coplanar waveguide is simulated to gain the optimum circuit performance. On the other hand, the broadband amplifier is implemented using the topology of three-stage cascaded single stage distributed amplifier to obtain the maximum gain in per unit area.
The measured and simulated results of the designed circuits are illustrated as followings: for the V-band LNA at 50 GHz, the obtained small signal gain is 20.7 dB, input power at the 1-dB gain compression point is -15 dBm, simulated noise figure is 4.2 dB at 60 GHz; for V-band coplanar waveguide LNA at 50 GHz, the small signal gain is 22.17 dB, output power at the 1-dB gain compression point is -18 dBm, the simulated noise figure is 5.2 dB at 60 GHz; for the 20-35 GHz cascaded single stage distributed amplifier, the small signal gain is more than 5 dB with a bandwidth of 15 GHz where the peak gain is 12.1 dB at 20 GHz, input power at the 1-dB gain impression point is -10 dBm and -7 dBm at 20 GHz and 28 GHz, respectively; for the 26-65 GHz cascaded single stage distributed amplifier, the small signal gain is more than 16.5 dB with a bandwidth of 39 GHz, input power at the 1-dB gain impression point is more than -15 dBm.

關鍵字(中)

★ 放大器
★ 寬頻
★ 低雜訊

關鍵字(英)

★ low noise
★ amplifier
★ broadband

論文目次

Abstract I
Table of Contents V
List of Tables VII
List of Figures VIII
Chapter 1 1
Introduction 1
1.1 Motivation 1
1.2 Amplifier Nonlinearity 2
1.3 Thesis Organization 5
Chapter 2 7
Noise Analysis 7
2.1 Introduction 7
2.2 Source of Noise 7
2.2.1 Thermal Noise 8
2.2.2 Shot Noise 9
2.2.3 Flicker Noise 9
2.3 Signal to Noise Ratio and Noise Figure 9
2.4 Noise in Linear Two-Port 12
2.5 Noise Figure of Cascaded Networks 22
Chapter 3 26
Design of Millimeter Wave Low Noise Amplifier 26
3.1 Introduction 26
3.2 Principle of Coplanar Wave Guide 27
3.2.1 Introduction 27
3.2.2 CB-CPW with Finite Width Ground Planes 28
3.2.3 Simulation of CPW with Finite-Width Ground Planes 31
3.3 V-band MMIC Low Noise Amplifier 37
3.3.1 Introduction 37
3.3.2 Circuit Structure and Design Flow 37
3.3.3 Simulated and Measured Results 43
3.3.4 Summary and Re-simulation 50
Chapter 4 55
Broadband Amplifier 55
4.1 Introduction 55
4.2 Distributed Amplifier Design 56
4.2.1 Conventional Distributed Amplifier 58
4.2.2 Cascaded Single Stage Distributed Amplifier 60
4.3 20-35 GHz Three-Stage CSSDA 63
4.3.1 Introduction 63
4.3.2 Circuit Structure and Design Flow 64
4.3.3 Simulated and Measured Results 67
4.3.4 Summary and Re-simulation 72
4.4 26-65 GHz Three-Stage CSSDA 74
4.4.1 Introduction 74
4.4.2 Circuit Structure and Design Flow 75
4.4.3 Simulated and Measured Results 77
4.4.4 Summary and Re-Simulation 83
Chapter 5 86
Conclusion and Future Work 86
Reference 88

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指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2006-7-19

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