具有自我對準下閘電極鍺量子點單電洞電晶體之研製

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徐紹華(Shao-hua Hsu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具有自我對準下閘電極鍺量子點單電洞電晶體之研製
(Germanium quantum-dot single-hole transistors with self-aligned electrodes based on a bottom-gate technology)

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摘要(中)

隨著CMOS製程技術進入奈米時代，電子元件的發展越來越趨向小尺寸、高操作速度、與低消耗功率，因此許多奈米元件越來越受到重視，其中單電子電晶體具有以上優點之外，更被認為可以應用於記憶體、邏輯電路以及量子訊息等方面，所以單電子電晶體已開始倍受矚目。而在單電子電晶體中最重要的核心技術除了形成奈米等級的量子點之外，還有自我對準之閘電極的製作，以利於閘極有效地調變量子點內部能階，並且減少閘極引起穿隧接面降低的寄生效應。另外，一般製作矽基材量子點與單電子電晶體通常使用Silicon on Insulator或者Silicon Germanium on Insulator的結構與超高解析度之電子束微影技術，但通常伴隨著高成本與製程掌控不易等缺點。本實驗室已成功開發出利用〝矽鍺選擇性氧化法〞氧化複晶矽鍺形成鍺量子點，這是一種具有經濟效益且與CMOS製程相容的方法。
本論文之研究重點為成功地在非晶矽與氮化矽表面沈積複晶矽鍺薄膜，克服複晶矽鍺沈積於二氧化矽表面時的潛伏期，利用〝矽鍺選擇性氧化法〞氧化複晶矽鍺形成鍺量子點並且利用下閘電極製作鍺量子點單電洞電晶體。在室溫下觀察到明顯的庫倫震盪電流，以及有效地抑制了閘極引起穿隧接面降低的寄生效應，並且經由光的激發可以觀察到更明顯的庫倫震盪。除此之外，觀察穿隧電流在不同偏壓與溫度下的變化，探討元件之不對稱現象與背景電流的發生機制。

摘要(英)

As CMOS technology is scaling into nanometer regime, the development of devices is towards small dimension, high speed, and low power consumption. Since single-electron (SE) device not only provide the aforementioned advantages but also could be applied to memory-devices, logic-devices and quantum information, the SE device has attracted lots of attention. In addition to forming a nano-scaled quantum dot (QD), it is also imperative for SE devices to form self-aligned gate and source/drain electrodes in order to manipulate the QD effectively and to suppress the gate-induced tunneling barrier lowering effect. However, the formation of SE devices from Silicon-on-Insulator(SOI) or SiGe-on-Insulator(SGOI) structures is usually with high cost and restricted design freedom. This motivates us to develop a simple method, “Selectivity oxidation of polycrystalline-SiGe” to form Ge QDs. It is a cost effective and CMOS compatible approach.
The main theme of this thesis is to suppress the large incubation time for poly-SiGe deposition onto silicon dioxide (SiO2) and to form uniform poly-SiGe thin film on amorphous-Si and silicon-nitride (Si3N4) surface. In addition, we make use of the selective oxidation of the poly-SiGe thin film to form uniformly distributed Ge QDs. Then we fabricate Ge-QD single-hole transistor (SHT) based on a bottom-gate technology. We have experimentally studied the electrical characteristics and photo-effect of the Ge-QD SHT. Clear Coulomb-blockade oscillation was observed at room temperature and the gate-induced tunneling barrier lowering effect is suppressed. Furthermore, enhanced Coulomb oscillation and peak-to-valley current ratio were realized under photo-excitation. Finally, we discussed the asymmetrical features and trap assisted carrier tunneling effect of this device.

關鍵字(中)

★ 複晶矽鍺
★ 鍺量子點
★ 單電子
★ 下閘電極
★ 庫倫阻斷

關鍵字(英)

★ single electron
★ bottom-gate
★ Coulomb-blockade
★ polycrystalline-SiGe
★ Ge quantum dot

論文目次

第一章研究動機...........................................1
1-1 半導體元件發展史......................................1
1-2 單電子電晶體的發展....................................2
1-3 單電子電晶體的應用....................................4
第二章單電子電晶體操作原理...............................7
2-1 前言.....................................7
2-2 單電子電晶體之操作原理................................7
2-2-1 能帶圖說明......................................7
2-2-2 調變source與drain的操作原理.....................8
2-2-3 調變gate的操作原理.............................10
2-3 以高摻雜半導體為電極的單電子電晶體之操作原理.........11
2-3-1 導電電子分佈範圍...............................11
2-3-2 負微分電導現象.................................11
第三章元件關鍵製程與開發................................21
3-1 前言..........................................21
3-2 複晶矽鍺薄膜沈積與鍺量子點之形成.....................21
3-2-1 沈積系統.......................................22
3-2-2 選擇性氧化矽鍺合金形成鍺量子點.................22
3-2-3 複晶矽鍺層沈積於二氧化矽層所面臨的問題.........23
3-3 複晶矽鍺薄膜沈積於二氧化矽層之實驗...................24
3-3-1 降低鍺莫耳含量.................................24
3-3-2 降低反應氣體流量...............................25
3-3-3 降低沈積溫度...................................25
3-3-4 營造利於沈積複晶矽鍺的背景.....................26
3-4 複晶矽鍺薄膜沈積於非晶矽層之實驗.....................27
3-5 複晶矽鍺薄膜沈積於氮化矽層之實驗.....................29
3-6 氧化複晶矽鍺薄膜形成鍺量子點與應用於元件之結果.......32
第四章單電洞電晶體製作流程..............................49
4-1 前言.................................................49
4-2 鍺量子點單電洞電晶體製作流程.........................49
第五章單電洞電晶體電性量測與分析........................62
5-1 Id-Vd特性與探討......................................62
5-2 Id-Vg特性與探討......................................64
5-2-1 背景電流隨著Vds偏壓提升........................64
5-2-2 溫度效應與探討.................................66
5-3 Gate induced tunneling barrier lowering effect之抑......67
5-4 穿隧接面中缺陷對載子傳輸的影響.......................67
5-5 光激發對穿隧電流之影響與探討.........................69
第六章總結與未來展望....................................80
參考文獻.................................................81

參考文獻

[1] 胡淑芬, “單電子電晶體簡介”, 奈米通訊, 第五卷, 第二期.
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指導教授

李佩雯(Pei-Wen Li)

審核日期

2007-10-16

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