應用在DDR2記憶體中之多相位輸出數位延遲鎖定迴路

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：76

、訪客IP：18.217.4.250

姓名

程震宇(Jhen-Yu Cheng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用在DDR2記憶體中之多相位輸出數位延遲鎖定迴路
(The Multiphase Digital-DLL for DDR2 Memory Application)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

隨著CMOS製程技術的進步，記憶體的複雜度及時脈訊號頻率均迅速增加，因此，系統內部同步時脈訊號之可靠度便愈來愈重要。如何消除時脈偏移(Clock Skew)的問題，將成為重要的議題。
本論文實現一個應用在雙通道兩次同步動態隨機存取記憶體（Double-Data-Rate Two Synchronous Dynamic Random Access Memory, DDR2 SDRAM）中之多相位（Multiphase）輸出數位延遲鎖定迴路（Digital Delay-Locked Loop, DDLL），利用數位編碼方式，控制延遲線中不同大小的MOS電容，產生不同的延遲訊號，達成延遲時間之粗調與細調的功能，以改進整體的鎖定時間、解析度與靜態相位誤差。且電路在鎖定後，能有效地在一個週期內產生八個平均相位輸出，故亦可應用於時脈倍頻器（Frequency Multiplier）或時脈資料復原（Clock Data Recovery, CDR）電路中。
本論文之DDLL架構中分為數位控制延遲線（Digital Control Delay Line, DCDL）、相位偵測器（Phase Detector, PD）、控制單元（Control Unit, CU）、上下數計數器(Up/Dn Counter)、編碼電路(Decoder)和資料取樣電路（Data Sample Circuit, DQS）等六個部分。在粗調延遲線中一開始初始在最小的延遲，來消除Harmonic Locking的現象，並利用單一方向性的操作，來避免Stuck Locking的方法，其操作範圍為（T/2～T）之間，符合兩倍操作頻率範圍。此數位延遲鎖定迴路是利用CMOS 0.13µm 1P8M之製程來實現，電路操作電壓為1.2V在製程為TT模式下溫度40℃時，工作頻率200MHz~410MHz，鎖定時間約在18個輸入週期內鎖定。其晶片的面積為830×640µm^2 (核心面積: 463×147µm^2, 0.065mm^2)，操作在頻率為410MHz時，其峰對峰值時脈抖動量（Peak-to-Peak Jitter）為7.8ps，功率消秏為3.5mW。

摘要(英)

To court high-frequency generation is coming with the evolution of CMOS process technology. The complexity and higher clock signal frequency of memory are increasing day after day. Therefore, the reliability of the clock signal in synchronous system becomes more and more important. How to reduce clock skew will be the most important topic of the clock synchronization circuit.
This thesis describes the digital delay lock loop（DDLL）with multiphase outputs that uses the decoder technique to produce various digital code to change the delay time of delay line. In order to improve the resolution and the locking time, it also uses MOS capacitance to achieve the circuits of coarse tune and fine tune. The DDLL with multiphase outputs for double-data-rate two synchronous dynamic random access memory（DDR2 SDRAM）application can eliminate clock skew of memory. Moreover, the DDLL with multiphase outputs can be used in frequency multiplier and clock data recovery（CDR）applications.
The proposed DDLL in this thesis is composed of the Digital Control Delay Line（DCDL）、Phase Detector（PD）、Control Unit（CU）、up/dn counter、decoder circuit and data sample circuit（DQS）. The initial delay of the coarse tune delay line is minimum delay time to eliminate the Harmonic Locking issue, and then it use single for direction to avoid Stuck Locking method. The operating range is (T/2～T) and accord with twice of the operating frequency range. This DDLL is implemented in a 0.13µm CMOS technology that can operate from 200 to 410MHz and the maximum lock time is 18 input clock cycles. The chip area is 830×640µm^2 with 463×147µm^2 core area.The peak-to-peak Jitter and power consumption at 410MHz are 7.8ps and 3.5mW, respectively.

關鍵字(中)

★ DDR2記憶體
★ 數位延遲鎖定迴路
★ 多相位輸出
★ 數位控制延遲鎖定迴路

關鍵字(英)

★ DDR2 Memory
★ Digital-DLL
★ Multiphase
★ DCDL

論文目次

第一章緒論 1
1.1 研究動機與目的 1
1.2 數位延遲鎖定迴路的應用 2
1.3 論文架構 2
第二章數位延遲鎖定迴路簡介 3
2.1 延遲鎖定迴路的分類 3
2.1.1 閉迴路式與開迴路式之設計 3
2.1.2 數位延遲鎖定迴路之電路設計架構分類 5
2.2數位延遲鎖定迴路之動作原理 7
2.3傳統數位延遲鎖定迴路架構簡介 9
2.3.1移位暫存器式延遲鎖定迴路 9
2.3.2計數器式延遲鎖定迴路 11
2.3.3漸近比較式數位延遲鎖定迴路 13
2.4數位延遲鎖定迴路的設計考量 15
2.5 數位延遲鎖定迴路內部子電路 21
2.5.1 粗調延遲元件(Coarse Tune Delay Cell)簡介 21
2.5.2 細調延遲元件(Fine Tune Delay Cell)簡介 25
2.5.3 控制負載元件設計（Controlled Load, CL）Cell Design 29
第三章數位延遲鎖定迴路設計與動作原理 31
3.1 數位延遲鎖定迴路架構 32
3.1.1 相位偵測器(Phase Detector) 33
3.1.2 控制單元(Control Unit) 34
3.1.3 計數器(Counter Circuit) 39
3.1.4 解碼器(Decoder Circuit) 40
3.2 數位延遲鎖定迴路操作原理 41
3.3 數位控制延遲線(Digital Controlled Delay Line) 42
3.3.1 粗調電路(Coarse Tune Circuit) 43
3.3.2 微調電路(Fine Tune Circuit) 46
3.3.3 製程變異補償電路(Corners Compensation Circuit) 48
第四章數位延遲鎖定迴路晶片實現與模擬 52
4.1數位延遲鎖定迴路模擬結果 52
4.2晶片佈局圖 64
4.3電路規格與比較表 66
4.4 測試考量 68
第五章結論 70
5.1 結論 70
5.2 未來改進方向 70
參考文獻 71

參考文獻

[1]B. Razavi, “Design of analog CMOS integrated circuit,” McGraw-Hill, Chap.15,2001.
[2]Z. Wang, and L. Liang, “An All Digital COMS Serial Link Transceiver with 3x Over-sampling Based Data Recovery,” The 6th International Workshop on System on Chip for Real Time Applications, pp.15-19, Dec. 2006.
[3]T.-T. Liu and C.-K. Wang, “A 0.8-8GHz 9.7mW Analog-Digital Dual-Loop Adaptive-Bandwidth DLL Based Multi-Phase Clock Generator,” Proceeding of the 30th European Solid-State Circuits Conference, pp. 375- 378, Sep. 2004.
[4]K.-H. Cheng, S.-M. Chang, and S.-Y. Jiang, “A 2GHz Fully Differential DLL-Based Frequency Multiplier for High Speed Serial Link Circuit,”IEEE International Symposium on Circuits and Systems, Japan, pp. 1174-1177, May. 2005.
[5]T. Saeki, Member and M. Tagishi, “A 1.3-Cycle Lock Time, Non-PLL/DLL Clock Multiplier Based on Direct Clock Cycle Interpolation for Clock on Demand,” IEEE J. Solid-State Circuits, vol. 35, no. 11, Nov. 2000.
[6]F. Lin, and R.-J. Baker, “A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM,” IEEE J. Solid-State Circuits, vol. 34, Apr. 1999.
[7]T. Hamamoto, Y. Konishi, and T. Yoshihara, “A 667Mb/s Operating Digital DLL Architecture for 512Mb DDR SDRAM,” IEEE J. Solid-State Circuits, vol. 39, no. 1, Jan. 2004.
[8]T. Saeki, and Nakanishi, “A 2.5ns Clock Access, 250MHz, 256Mb SDRAM with Synchronous Mirror Delay,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1656 - 1668, Nov. 1996.
[9]G. Kim, M.-K. Kim, and B.-S. Chang, W. Kim, “A Low-Voltage, Low Power CMOS Delay Element,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 966- 971, Jul. 1996.
[10]G.-K. Dehng, and S.-I. Lin, “A Fast-Lock Mixed-Mode DLL Using a 2-b SAR Algorithm,” IEEE J. Solid-State Circuits, vol. 36, no. 10, Oct. 2001.
[11]C.-C. Chung and C.-Y. Lee, “A New DLL-Based Approach for All-Digital Multiphase Clock Generation,” IEEE J. Solid-State Circuits, vol. 39, no. 3, Mar. 2004.
[12]R.-J. Yang and S.-I. Liu, “A 40-550MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm,” IEEE J. Solid-State Circuits, vol. 42, no. 2, Feb. 2007.
[13]G.-K. Dehng and S.-I. Liu, “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 35, no. 8, Aug. 2000.
[14]C.-S. Hwang, and S.-I. Liu, “A 2V Clock Synchronizer using Digital Delay-Locked Loop,” The second IEEE Asia Pacific Conference on ASICs, pp. 91-94, Aug. 2000.
[15]J. G. Maneatis and M. A. Horowitz, “Precise Delay Generation Using Coupled Oscillators,” IEEE J. Solid-State Circuits, vol. 28, no. 12, Dec. 1993.
[16]P.-L. Chen, C.-C. Chung, and C.-Y. Lee, “A Portable Digitally Controlled Oscillator Using Novel Varactors,” Teansactions on Circuits and Systems-II：Express Briefs, vol. 52, no. 5, May. 2005.
[17]M.-N. Mohammad, and M. Sachdev, “A Monotonic Digitally Controlled Delay Element,” IEEE J. Solid-State Circuits, vol. 40, no. 11, Nov. 2005.
[18]C.-C. Chung, P.-L. Chen, and C.-Y. Lee, “An All-Digital Delay-Locked Loop for DDR SDRAM Controller Applications,” in International Symposium on VLSI Design, Automation and Test, pp. 1-4, 2006.
[19]Y.-J. Wang, S.-K. Kao, and S.-I. Liu, “All-Digital Delay-Locked Loop/Pulsewidth-Control Loop with Adjustable Duty Cycles,” IEEE J. Solid-State Circuits, vol. 41, no. 6, Jun. 2006.
[20]T. Matano, Y. Takai, and K. Koyama, “A 1Gb/s/pin 512Mb DDR2 SDRAM Using a Digital DLL and a Slew-Rate-Controlled Output Buffer,” IEEE J. Solid-State Circuits, vol. 38, no. 5, Jan. 2003.
[21]R.-J. Yang and S.-I. Liu, “A 2.5GHz All-Digital Delay-Locked Loop in 0.13μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 42, no. 2, Feb. 2007.
[22]S. Eto, and T. Seki, “A 333MHz, 20mW,18ps Resolution Digital DLL using Current-controlled Delay with Parallel Variable Resistor DAC (PVR-DAC),” Asia Pacific Conference on ASICs, pp.349-350, Aug. 2000.
[23]H.-H. Chang, J.-Y. Chang, and S.-I. Liu, “A 0.7-2GHz Self-Calibrated Multiphase Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 41, no. 5, May. 2006.
[24]L. Chen, G. Ou, and X.-j. Zeng, “Digital 90-degree Phase Shifter without PLL or DLL,” in International Conference on Solid-State and Integrated Circuit Technology, 2006.
[25]J.-J. Jong, and C.-Y. Lee, “A Novel Structure for Portable Digitally Controlled Oscillator,” in International Symposium on Circuits and Systems, pp. 272-275, 2001.
[26]K.-H. Cheng, and Y.-L. Lo, “A Fast-Lock Mixed-Mode DLL with Wide-Range Operation and Multiphase Outputs,” IEEE Teansactions on Circuits and Systems-II：Express Briefs, vol. 54, no. 7, pp. 561-565, Jul. 2007.
[27]K-H. Cheng, and Y.-L. Lo, “A Fast-Lock DLL with Power-On Reset Circuit,” International Symposium on Circuits and Systems, vol.4, pp. IV-357-360, May. 2004.
[28]B.-S. Kim, and L.-S. Kim, “A Low Power 100MHz All Digital Delay-Locked Loop,” International Symposium on Circuits and Systems, pp. 1820-1823, Jun. 1997.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2008-4-29

推文