實現在90奈米製程1伏特十位元每秒二十億次取樣採用精確參考電流源之數位類比轉換器

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王信濠(HSIN-HAO WANG) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

實現在90奈米製程1伏特十位元每秒二十億次取樣採用精確參考電流源之數位類比轉換器
(1-V 10-bit 2GSample/s D/A Converter based on Precision Current Reference in 90-nm CMOS)

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摘要(中)

現今通訊系統的應用中，對於高速操作與資訊流量的要求日益增加，此外因為SoC整合的需求，數位類比轉換器與數位信號處理電路的整合逐漸成為未來系統發展上一股重要的趨勢，因此電路實現上也勢必走向使用更先進的製程，針對於以上需求，本論文提出一項能應用於90奈米製程，低操作電壓、高速及高精準度的數位類比轉換器。
為了能達到高速運作的需求下，本文採取全差動電流式切換數位類比轉換器之架構，其中數位電路部份是以電流模式邏輯電路的架構來呈現，使得電路在邏輯切換時能得到較高的轉換速度，並能有效降低電路產生的偶次諧波失真與電源上的電壓抖動量。
在類比電路部份，因面臨低供應電壓及電晶體短通道效應之影響，使得在設計準確的電流源矩陣將變得非常因難，所以我們提出一個新的高準確主動式疊接電流鏡射架構，以提供電流源在切換的過程中，可同時確保電流之精確度，並能克服操作於1伏特時，輸出電壓振幅被壓縮及電流源輸出阻抗被嚴重限制之問題。
在晶片的實現上，本論文提出一個取樣頻率2GS/s之十位元數位類比轉換器，並實現在90nm CMOS 1P9M製程且操作電壓為1伏特。其中INL誤差範圍於±0.32LSB之內，而DNL誤差範圍於±0.13LSB，且輸入9.3MHz之數位碼時SFDR為65.1dB，而在982.2MHz時SFDR為54.4dB，整體的功率消耗為79mW，核心面積為 0.6mm × 0.416mm。上述規格已在晶片的模擬驗證上，證實此架構之可行性。

摘要(英)

Nowadays the communication applications call for high speed operation. At the same time the SoC era continuously goes on, integrating digital-to-analog converter (DAC) with DSP becomes an important tendency. In view of this, this thesis proposes a digital-analog converter which can apply to 90um CMOS technology with low supply voltage、high speed and high solution applications.
For high speed operation, the work employed a fully differential architecture. The logic operation of the digital circuits must match the DAC so as to achieve the faster conversion rate. Therefore current mode logic (CML) is often used in the high speed logic design. Besides, CML can effectively reduce the even harmonics distortion and power-ground bounce.
In analog circuit part, output impedance is restricted by the low supply voltage and MOS short-channel effect. Designing an accurate current mirror for current source matrix, therefore, becomes extremely difficult. For 1 volt supply voltage considering the demands, a DAC with a new high precision active cascode mirror circuit is proposed in this work. The precision of this current source array can be obtained. In addition, the demand of low supply voltage and the influence of MOS short-channel effect can be overcome.
The proposed 2GS/s 10bit DAC is implemented in 90nm CMOS 1P9M technology with the supply voltage of 1 volt. The INL is ±0.32LSB, and the DNL is ±0.13LSB. When the DAC operates at an input signal frequency of 9.3MHz, a SFDR of 65.1dB can be achieved. Moreover, a SFDR of 54.4dB can be gained when the DAC operates at 982.2MHz. The power consumption of the proposed design is 79mW. The core area is 0.6mm × 0.416mm

關鍵字(中)

★ 數位類比轉換器
★ 十位元
★ 參考電流源
★ 90奈米

關鍵字(英)

★ DAC
★ 2G
★ 1V
★ 90nm
★ 10bit
★ current reference

論文目次

第一章緒論....1
1.1 研究背景....1
1.2 研究動機....1
1.3 論文架構....2
第二章數位類比轉換器基本原理....3
2.1 簡介....3
2.2 理想數位類比轉換器....3
2.3 數位類比轉換器規格參數定義....3
2.3.1 靜態參數(Static Parameters)....4
2.3.1.1 解析度(Resolution)....5
2.3.1.2 偏移誤差(Offset Error)....5
2.3.1.3 增益誤差(Gain Error)....6
2.3.1.4 差動非線性誤差(Differential Nonlinearity Error,DNL)....6
2.3.1.5 累積非線性誤差(Integral Nonlinearity Error,INL)....7
2.3.1.6 單調性(Monotonicity)....8
2.3.2 傳輸參數(Transmission Parameters)....8
2.3.2.1 穩定上升及下降時間(Settling Rise and Fall Time)....8
2.3.2.2 突波(Glitch)....9
2.3.2.3 轉換時間(Conversion Time)....9
2.3.3 動態參數(Dynamic Parameters)....10
2.3.3.1 信號對雜訊比(Signal-to-Noise Ratio)....10
2.3.3.2 信號對雜訊及諧波失真比 (Signal-to-Noise and Distortion Ratio)....10
2.3.3.3 總諧波失真 (Total Harmonic Distortion)....11
2.3.3.4 有效位元數 (Effective Number of Bits)....11
2.3.3.5 SFDR (Spurious Free Dynamic Range)....11
第三章數位類比轉換器基本架構....12
3.1 電阻串列式數位類比轉換....12
3.2 兩級串列電阻式數位類比轉換器....13
3.3 二進碼權重電阻式數位類比轉換器....14
3.4 電容電荷重新分布式數位類比轉換器....15
3.5 R-2R電阻階梯式數位類比轉換器....16
3.6 電流切換式數位類比轉換器....17
3.6.1 二進位碼權重電流切換式數位類比轉換器....18
3.6.2 溫度計碼電流切換式數位類比轉換器....19
3.6.3 分段式電流切換式數位類比轉換器....21
第四章數位類比轉換器設計考量....22
4.1 Current Steering DAC 的設計考量....22
4.2 SNDR與Mismatch的關係....22
4.3 元件與Mismatch的分析....26
4.4 INL&DNL分析....27
4.5 動態參數SFDR之分析....28
4.6 動態參數SNDR之分析....30
4.7 雜訊分析....32
4.8 電流源頻寬設計考量....34
4.9 分段式考量....36
4.10 數位電路的設計考量....38
4.10.1 MOS電流型式邏輯....38
4.10.2 二進碼轉溫度計碼編碼電路....39
4.10.3 Pipeline設計方式....42
4.11 突波設計考量....42
4.11.1 數位控制訊號不同步....43
4.11.2 電流切換時開關同時出現關閉....44
4.12 電流源佈局考量....45
4.12.1 線性梯度誤差(Linear Gradient Error)....46
4.12.2 拋物線梯度誤差(Parabolic Gradient Error)....47
第五章電路實現與模擬結果....49
5.1 電流源電路....49
5.2 定電流電路....51
5.3 高準確性主動式疊接電流源鏡射架構....52
5.3.1 電流源偏壓平均化設計....52
5.3.2 高準確性主動式疊接電流鏡射架構....53
5.3.3 高增益主動式運算放大器電路....56
5.4 Current Steering 數位類比轉換器電路實現....58
5.5 Current Steering 數位類比轉換器模擬結果....58
5.5.1 靜態參數的模擬....59
5.5.2 動態參數的模擬....63
5.6 晶片佈局圖....70
5.7 規格與效能比較....73
5.8 量測考量....74
第六章結論....76
6.1 總結....76
6.2 未來展望....77
參考文獻....78

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2008-4-29

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