| 摘要(英) |
With the advance of semiconductor process, the supply voltage of a chip has been shrunk to 1.2v, even less than 1v. In such designs, I-R drop noise on power lines becomes more serious due to it’s increasing ratio. Therefore, power noise analysis has become one of the most important issues in modern design flow. However, traditional power noise analysis can be performed at transistor level only, even at physical level. If power noise problems occur at such a late stage, the redesign cost is very expensive
In this thesis, we propose a high-level IR-drop estimation technique to analyze supply noise at early design stages. Since high-level current waveform modeling has been developed, we propose a transformation process to translate the ideal current waveform into the current waveform with IR-drop effects. Then, the voltage drop on power lines can be obtained very quickly from the none-ideal current waveform. Therefore, this could be a convenient early verification approach for designers to estimate the IR-drop of power lines. |
| 參考文獻 |
參考文獻
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