應用於6 GHz時脈產生器之高解析度抖動量測電路

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：75

、訪客IP：18.223.211.203

姓名

李昱良(Yu-liang li) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於6 GHz時脈產生器之高解析度抖動量測電路
(On-Chip High Resolution Jitter Measurement Circuit for 6 GHz Clock Generator)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

隨著半導體製程技術不斷的進步，積體電路單晶片化的系統已成趨勢，當系統整合時，電路上同步時脈訊號的重要性便日益彰顯，若時脈的抖動量過大或具相位偏移時，會造成系統在操作上錯誤。有鑑於此，此系統上便選擇鎖相迴路(Phase-Locked Loop ,PLL)或延遲鎖定迴路(Delay-Locked Loop , DLL)來當作參考時脈來源，但就目前單晶片化的趨勢與操作頻率不斷的提升，要直接針對鎖相迴路或延遲鎖定迴路的輸出時脈信號抖動量進行量測已變成相當困難，此外利用外部儀器量測不僅需花費高額的成本，再加上外部儀器在進行量測時會引入雜訊，影響其結果，基於上述原由，內建自我測試電路便因此產生。
本論文提出的「應用於6 GHz時脈產生器之高解析度抖動量測電路」以提高量測解析度、降低製程變異影響為設計準則，本論文採用自我取樣的方式搭配具多相位取樣電路的作法改善傳統抖動量測電路需額外信號作為參考信號源。此外為了能夠量測到時脈信號微小抖動量，在電路中加上時間放大電路(Time Amplifier Circuit)以提高量測的精準度。
本次抖動量測電路是利用TSMC 90 nm 1P9M製程來設計，完成應用6 GHz時脈產生器之高解析度抖動量測電路，解析度可逹到1 ps左右。

摘要(英)

As the improvement of semiconductor technology, VLSI circuit has developed in a system on chip (SoC). If the clock jitter is excessive or phase deviation, the mistakes of system operation will be enerated. In view of this problem, clock synchronization circuits such as PLLs and DLLs will be used the clock source. But on a tendency toward SoC system and high operating speed, it is difficult to measure the output clock jitter of the PLL circuit directly. In addition, using external measuring equipments not only need to take the high cost of equipment and noise caused by the test results also affected. For these reasons, the built-in self-test circuitry for clock jitter measurement can be produced.
This thesis on-chip high resolution jitter measurement circuit with self-calibration technique for 6 GHz clock generator is proposed to improve the measurement resolution. It can reduce process variation effect. The conventional jitter measurement circuits need an additional signal as the reference source. In this thesis, the use of self-refereed method with multi-phase sampler can eliminate the problems of the reference source. It also reduces the circuit mismatch. In addition, in order to measure the tiny clock jitter in high-speed serial link, the proposed circuit uses the time amplifier circuit to increase the high accuracy. However, process variation will also influence the measure results. Therefore, the first auto-calibration and second calibration circuits are used to compensate the process variation.
This jitter measurement circuit is designed in TSMC90nm 1P9M process. It can measure the 6GHz clock jitter. The resolution of the overall circuit is 1ps .

關鍵字(中)

★ 高解析度抖動量測電路

關鍵字(英)

★ High Resolution Jitter Measurement Circuit

論文目次

目錄
摘要.. I
Abstract.. II
目錄 III
圖目錄 V
表目錄 VI
第一章緒論 1
1.1 研究動機 1
1.2 論文架構 2
第二章時脈抖動基本定義 3
2.1 時脈抖動的基本定義 3
2.2 時脈抖動的類別 4
2.2.1 週期對週期時脈抖動 4
2.2.2 週期性時脈抖動 5
2.2.3 長期性時脈抖動 6
2.3 時脈抖動分佈圖 7
第三章時脈抖動量測方法 10
3.1 OFF-CHIP外部時脈抖動量測方式 10
3.2 ON-CHIP內部時脈抖動量測方式 12
3.3 ON-CHIP內部時脈抖動量測電路介紹 13
3.3.1 時間數位轉換器 13
3.3.2 延遲串列方法 14
3.3.3 游標尺延遲線方法 15
3.3.4 改良式游標尺延遲線方法 17
3.3.5 游標尺環形振盪器方法 17
3.3.6 脈衝縮減量測法 19
第四章具多相位環形振盪器之抖動量測電路設計 20
4.1 抖動量測電路架構圖 20
4.2 具多相位環形振盪器之抖動量測電路實現 21
4.2.1 自我取樣電路 22
4.2.2 時間放大電路 24
4.2.3 多相位取樣電路 25
4.2.3.1 基板控制正反器 25
4.2.3.2 多相位環形振盪器 27
4.2.4 計數器 28
4.2.5 校正電路 28
4.2.5.1 第一級校正電路 29
4.2.5.2 第二級校正電路 30
4.3 電路操作 31
4.3.1 校正模式 32
4.3.2 量測模式與規格訂定 35
第五章晶片實現與模擬 35
5.1 設計流程介紹 36
5.2 電路模擬結果 36
5.2.1 自我取樣電路 37
5.2.2 時間放大電路 38
5.2.3 多相位環形振盪器 38
5.2.4 切換式移位暫存器 39
5.2.5 校正電路 41
5.2.6 抖動分佈 40
5.3 電路規格與比較 41
5.4 電路佈局與模擬驗證 42
5.4.1 電路佈局 42
5.4.2 模擬驗證 44
第六章結論 44
6.1 結論 44
6.2 未來改進方向 44
參考文獻 44

參考文獻

參考文獻
[1] F. Azais, M. Renovell, Y. Bertrand, A. Ivanova, and S. Tabatabaei, “A Unified Digital Test Technique for PLLs: Catastrophic Faults Covered,” Proc. of Int. Mixed Signal Testing Workshop, pp. 269-292, Jun. 1999.
[2] K. A. Taylor, B. Nelson, A. Chong, H Lin, E. Chan, M. Soma, H. Haggag, J. Huard, J. Braatz, “Special Issue on BIT CMOS Built-In Test Architecture for High-Speed Jitter Measurement,” IEEE Trans. on Instrumentation and Measurement, vol.54, no.3, pp. 975-987, Jun. 2005.
[3] B. Kaminska, “BIST means more measurement options for designers,” EDN Magazine, Dec. 2000.
[4] K. Ichiyama, M. Ishida, T. J. Yamaguchi, and M. Soma, “An On-chip Delta-time-to-voltage Converter for Real-Time Measurement of Clock Jitter,” IEEE International Symp. on Circuits and Systems, pp. 2798-2801, May 2007.
[5] T. Xia, and J. Lo, “Time-to-voltage Converter for On-chip Jitter Measurement,” IEEE Trans. on Instrumentation and Measurement, pp. 1738-1748, Dec. 2003.
[6] A. H. Chan, and G. W. Roberts, “A Jitter Characterization System Using a Component-invariant Vernier Delay Line,” IEEE Transactions on VLSI Systems, vol.12, pp. 79-95, Jan. 2004.
[7] P. Dudek, S. Szczepanski, and J. Hatfield, ” A High-resolution CMOS Time -to-digital Converter Utilizing a Vernier Delay Line,” IEEE J. Solid-state Circuits, vol.35, pp. 240-247, Feb. 2000.
[8] A. H. Chan, and G.W. Roberts “A Deep Sub-micron Timing Measurement Circuit Using a Single-Stage Vernier Delay Line,” IEEE Proc. CICC, pp. 77-80, May 2002.
[9] P. Chen, S. Liu, and J. Wu, “A Low Power High Accuracy CMOS Time-to-digital Converter,” IEEE Proceeding of ISCAS, pp. 281-284, 1997.
[10] T. Xia, H. Zheng, J. Li, and A. Ginawi, “Self-refereed On-chip Jitter Measurement Circuit Using Vernier Oscillators,” IEEE Computer Society Annual Symposium on VLSI, pp. 218-213, May 2005.
[11] M. Lee, and A. A. Abidi, “A 9b, 1.25ps Resolution Coarse-fine Time-to-digital Converter in 90 nm CMOS that Amplifies a Time Residue,” IEEE J. Solid-state Circuits, vol.43, no.4, APR. 2008
[12] H. Y. Huang and J. F. Lin, “Design and Application of CMOS Bulk Input Scheme,” IEEE J. Solid-State Circuits, pp. 1305-1312, Aug. 2004.
[13] J. G. Maneatis, and M. A. Horowitz, “Precise delay generation using coupled oscillators,” IEEE J. Solid-state Circuits, vol. 28, pp. 1273-1282, Dec. 1993.
[14] L. Sun, T. Kwasniewski, and K. Iniewski, “A qquadrature output voltage controlled ring oscillator based on three-stage subfeedback loops,” in Proc. IEEE Int. Symp. Circuits and Syst. (ISCAS), vol. 2, 1999, pp. 176–179.
[15] K. Sung, and L. S. Kim, “A High-resolution Synchronous Mirror Delay Using Successive Approximation Register,” IEEE J. Solid-state Circuits, vol. 39, no. 11, pp. 1997-2004, Nov. 2004.
[16] M. A. Abas, G. Russell, and D. J. Kinniment, “Embedded High-resolution Delay Measurement System Using Time Amplification,” IEEE Institution of Engineering of Technology Computers & Digital Techniques, pp. 77-86, Mar. 2007.
[17] S. Sunter and A. Roy, “On-chip Digital Jitter Measurement, from Megahertz to Gigahertz,” IEEE Design & Test of Computers, pp. 314-321, Jul. 2004.
[18] Agilent, “Agilent Infiniium Oscilloscope Jitter Analysis Technique.”
[19] T. Xia, H. Zheng and J. Li, “Self-refereed on-chip jitter measurement circuit using Vernier oscillators,” in Dig. Tech. Papers IEEE Symp. VLSI Circuits, pp. 218-223, May 2005.
[20] K. Nose, M. Kajita and M. Mizuno, “A 1ps-resolution jitter measurement macro using interpolated jitter oversampling,” in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, 2006, pp.2112–2121.
[21] J. C. Hsu and C. C. Su, “BIST for measuring clock jitter of charge-pump phase-locked loops,” IEEE Trans. Instrum. Meas., vol. 57, no. 2, pp.276–284, Feb. 2008.
[22] K. H. C., S. Y. J., and P. Y. J.,“2.5GHz Built-in Jitter Measurement System in a Serial-Link Transceiver,” IEEE Trans. on VLSI systems , Jan. 2009

指導教授

鄭國興

審核日期

2009-7-31

推文