部分平行低密度同為元檢查碼解碼器設計

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姓名

吳佳俊(Chia-chun Wu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

部分平行低密度同為元檢查碼解碼器設計
(A Partially Parallel Low-Density Parity Check Code Decode)

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摘要(中)

摘要
LDPC解碼演算法是使用訊息傳遞(Message passing)；要獲得高效率的解碼情況下，在解碼硬體實現上必須使用大量的記憶體來儲存交換的訊息，而所需的記憶體大小跟同位元矩陣(H matrix)中1的數目有關。換句話說，當同位元矩陣架構越大的話則所需要的記憶體也會增加。
部分平行架構的兩種記憶體使用方法，共享記憶體架構與獨立型記憶體架構已普遍實施於LDPC解碼器。過去的研究提出了一種替代的方法，大大減少了記憶體大小的需求。在本論文中，提出使用移位暫存器用來取代記憶體，並以資料取回電路，進一步提
高吞吐量。結果顯示，本論文LDPC碼解碼器，在碼長為1536和編碼率為1 / 2，頻率為380MHz時吞吐率可達到124 Mbps。

摘要(英)

Abstract
LDPC decoding algorithm is a result of the use of Message passing Concept way, obtain efficient decoding circumstances, the realization of the decoder hardware, with plenty of memory to store the messages exchanged, required memory size with the same H matrix contains the number of 1. In other words, When the H Structure, then the greater the need will increase memory.
Two partially parallel architectures have been commonly implemented for LDPC decoders: Share-memory architecture and Individual-memory architecture. Our previous study has presented an alternative approach that significantly reduces the memory size requirement. In this study, shift-registers are employed to replace memory to simplify the data retrieval scheme and to further improve the throughput. Results show that the a LDPC decoder, with a code length of 1536 and a code rate of 1/2, can achieves the data rate up to 166 Mbps at the maximum clock frequency of 460 MHz.

關鍵字(中)

★ 低密度同位元檢查碼解碼設計
★ 檢查碼

關鍵字(英)

★ Low-Density Parity Check Code Decode
★ LDPC

論文目次

目錄
摘要.....i
Abstract.....ii
圖目錄.....v
表目錄.....vii
一、緒論.....1
1.1研究動機.....1
1.2低密度同位檢查碼(LDPC)簡介.....2
1.3LDPC編碼方式.....5
1.4類迴旋H矩陣 (Quasi-Cyclic H matrix).....6
二、LDPC解碼演算法.....8
2.1LDPC解碼演算法(LDPC Decode Algorithm).....8
2.2訊息傳送演算法(Message Passing Algorithm).....8
2.2.1積和演算法(Sum-product Algorithm).....9
2.2.2對數型積和演算法(Log-Likelihood Ratio for Sum-Product Algorithm, LLR-SPA).....14
2.2.3最小和演算法(Min-Sum Algorithm).....15
三、解碼器硬體架構.....17
3.1 LDPC解碼架構.....17
3.1.1完全平行架構(Fully parallel Architecture).....17
3.1.2序列架構(Serially Architecture).....18
3.1.3部分平行架構(Partially parallel Architecture).....19
3.1.4探討.....21
3.2CNFU與BNFU 架構.....22
3.2.1對數型積和演算法硬體架構.....22
3.2.2最小和演算法硬體架構.....23
3.3減少記憶體方法(Memory reduction method ).....25
3.3.1改良型最小和演算法(Modify Min-Sum Algorithm).....25
3.3.2記憶體排列方式(Memory arrangement).....28
四、提出的架構設計與電路實現.....31
4.1資料取回結構Data Retrieval Scheme.....31
4.1.1資料取回結構問題.....31
4.1.2資料取回方式.....32
4.2 提出的資料取回結構.....33
4.2.1提出的移位暫存器流程.....33
4.2.3提出的解碼方塊圖.....36
4.2.4提出的CSR演算法.....37
4.2.5 CSR探討.....39
4.3硬體架構.....39
4.3.1整體解碼架構(Overall decoding architecture).....39
4.3.2處理器(Process Unit, PU).....40
4.3.3最小值搜索(Minimum Value Find,MVF).....42
4.3.4提出的記憶體排列方式.....44
4.3.5環型移位暫存器(Circular Shift Register,CSR).....45
4.4實驗結果(Experimental Results).....45
五、結論與未來工作..... 49
5.1總結與結論.....49
5.2未來工作.....50
參考文獻.....51

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指導教授

魏慶隆(Chin-Long Wey)

審核日期

2009-8-16

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