使用電流級距控制器以達到寬操作頻率範圍之數位式鎖相迴路

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姓名

張毓玲(Yu-Ling Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

使用電流級距控制器以達到寬操作頻率範圍之數位式鎖相迴路
(A Digital PLL Using Current-Step Controller for Wide Operating Range Application)

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摘要(中)

本論文提出具寬操作頻率範圍之數位式鎖相迴路，其架構採用數位迴路濾波器取代由電阻及電容所組成之被動濾波器，以達到降低面積之效果；同時利用降低數位迴路濾波器取樣頻率之方法，使其在輸入參考頻率與除頻器之除數同時變動時，鎖相迴路系統皆為穩定操作。其中，使用所提出的具有電流級距控制器之數位至電流轉換器，除了使數位控制振盪器之轉換增益較為線性外，同時也可提高其頻率調控之解析度，達成低時脈抖動之設計。
此數位式鎖相迴路採用台積電 0.18 um 1P6M CMOS製程實現，並經由量測驗證其操作頻率範圍可達到200 MHz至1.4 GHz，且在操作頻率為800 MHz時，其峰對峰時脈抖動量(peak-to-peak jitter)為4.6%。其在供應電壓為1.8 V且輸出時脈為1 GHz之操作下消耗功率為7.27 mW，核心面積為0.04 mm2。此數位式鎖相迴路在與相同輸出頻率的倍頻範圍條件相比下，所耗費之面積極小，因此極為適合於系統晶片之應用。

摘要(英)

In this thesis, a digital phase-locked loop (DPLL) with the wide operating range is presented. The architecture of the proposed DPLL uses a digital loop filter to replace passive loop filter for area saving purpose. The DPLL maintains the system stability by reducing the sampling frequency when the reference clock and the multiplication factor are varied. The linearity of the gain and timing resolution of digital-controlled oscillator are improved by using the proposed digital-to-current converter with current-step controller (CSC). Thus, the CSC used here can enhance the jitter performance.
The proposed DPLL is implemented in a 0.18-um TSMC 1P6M CMOS process. It can operate from 200 MHz to 1.4 GHz and has a 4.6% peak-to-peak jitter at 800 MHz. The power consumption and the core area are 7.27 mW at 1 GHz and 0.04 mm2, respectively. In this work, the proposed DPLL can obtain the small area cost under the same multiplication range. Therefore, it is useful for system on chip (SoC) systems.

關鍵字(中)

★ 可調變除數之除頻器
★ 寬操作頻率範圍
★ 數位迴路濾波器
★ 電流級距控制器
★ 數位至電流轉換器
★ 頻率合成器
★ 鎖相迴路
★ 時間至數位碼轉換器

關鍵字(英)

★ programmable divider
★ wide operating frequency range
★ digital loop filter
★ digital-to-current converter
★ current-step controller
★ time-to-digital converter
★ phase-locked loop (PLL)
★ Frequency synthesizers

論文目次

圖目錄 vi
表目錄 ix
第1章導論 1
1.1 鎖相迴路之應用 1
1.2 研究動機 2
1.3 論文組織 3
第2章鎖相迴路先前技術探討 4
2.1 鎖相迴路種類簡介 4
2.1.1 線性式鎖相迴路 4
2.1.2 數位式鎖相迴路 5
2.1.3 全數位式鎖相迴路 5
2.2 可攜式之全數位式鎖相迴路 [6] 6
2.3 動態串聯頻率計數迴路之全數位式鎖相迴路 [7] 8
2.4 自我偏壓之高除數之數位式鎖相迴路 [8] 9
2.5 具動態快速追鎖頻率漂動之數位式鎖相迴路 [9] 11
第3章鎖相迴路系統分析 14
3.1 數位式鎖相迴路分析 14
3.2 全數位式鎖相迴路分析 17
3.3 MATLAB之模擬與探討 22
第4章數位式鎖相迴路實現 27
4.1 電路架構 27
4.2 具有電流級距控制器之數位至電流轉換器 28
4.3 電流控制振盪器 31
4.4 時間至數位碼轉換器 33
4.5 數位迴路濾波器 37
4.6 相位頻率偵測器 39
4.7 可調變除數之除頻器 41
4.8 鎖相迴路模擬結果 43
第5章晶片佈局與測試考量 44
5.1 晶片佈局考量 44
5.2 晶片佈局後模擬 47
5.2.1 晶片佈局後模擬結果 47
5.3 晶片測試考量 54
5.4 量測結果 57
第6章總結與未來展望 63
6.1 總結 63
6.2 未來研究方向 64
參考文獻 65

參考文獻

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2010-1-21

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