矽單晶轉移薄膜層表面埃級平滑化之研究

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姓名

蘇雅惠(Ya-hui Su) 查詢紙本館藏

畢業系所

機械工程學系

論文名稱

矽單晶轉移薄膜層表面埃級平滑化之研究
(An Angstrom-Scale Surface Smooth Technology for Transferred Single-Crystal Silicon Thin Film Layers)

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摘要(中)

為製作單晶矽層具有奈米等級的SOI材料，利用氫離子聚合為基礎的單晶矽層之薄膜轉移法已被普遍應用，但由於矽單晶薄膜於轉移之後，會在其轉移層上方形成一層粉碎層，因此通常於製程後需要再多一道化學機械研磨(CMP)的拋光步驟來將此粉碎層移除。而本研究目的主要在於利用蝕刻的方式，藉由特定之蝕刻液，於特定溫度下，將以智切法轉移後之SOI薄膜表層的粉碎層去除，同時達到表面平滑的效果，避免掉CMP程序，以簡化製程。研究中成功的以多晶矽犧牲層的沉積來改善氫離子佈植時通道效應的發生，減緩氫離子植入時穿透進矽基板的深度差，使得剝離後之SOI薄膜的表面粗糙度獲得初步地改善。之後藉由蝕刻將粉碎層移除，使得表面粗糙度更進一步地降低，以此兩個階段完成矽單晶轉移薄膜層的表面平滑化。

摘要(英)

The technique of single-crystal Si layer transfer based on using Hydrogen ion implantation has been widely applied in the fabrication of SOI materials possessing nano-scale device layer with single-crystal quality. However, after Si layer transfer process, a lattice-defect region was formed near the surface of transferred Si layer. Therefore, this unwanted region usually needs an extra chemical mechanical polishing (CMP) process to remove it. The main purpose of this study is to avoid the above polishing process as well as simplify the manufacturing processes. In this study, the removal of lattice-defect region generated after layer transfer by Smart-cut® method used etching approach with specific etchants to etch out it at specific temperature. This etching process could also result in surface smooth of the Si transferred layer. Besides, depositing a polysilicon layer as a sacrificial layer has successfully improved the occurrence of channel effect during ion implantation process and then reduced the difference of ion penetration depth to initially modify the surface roughness of the as-split SOI thin film. The surface roughness could be further decreased after using etching approach to remove the lattice-defect region. The above two steps can make the final surface of the transferred single-crystal Si layer smooth and uniform.

關鍵字(中)

★ 矽單晶
★ 蝕刻
★ 薄膜轉移
★ 表面平滑

關鍵字(英)

★ SOI
★ Surface Smooth
★ Layer Transfer
★ etching

論文目次

中文摘要..................................................I
英文摘要.................................................II
誌謝....................................................III
目錄.....................................................IV
圖目錄...................................................VI
表目錄...................................................IX
一、緒論.................................................1
1.1 研究背景.............................................1
1.2 研究動機.............................................3
二、文獻回顧.............................................4
2.1 絕緣層矽晶薄膜之特性.................................4
2.2 絕緣層矽晶圓之製程技術...............................6
2.3 單晶奈米絕緣層矽薄膜之平滑技術.......................9
三、蝕刻機制............................................25
3.1 乾式蝕刻(Dry Etching)...............................25
3.2 濕式蝕刻(Wet Etching)...............................27
3.2.1 等向性濕式蝕刻.....................................29
3.2.2 非等向性濕式蝕刻...................................30
四、實驗方法及步驟......................................37
4.1 實驗流程............................................37
4.1.1 試片準備及清洗.....................................37
4.1.2 結晶矽薄膜沉積.....................................37
4.1.3 離子佈植...........................................39
4.1.4 多晶矽蝕刻.........................................40
4.1.5 晶圓鍵合...........................................40
4.1.6 薄膜轉移...........................................41
4.1.7 SOI薄膜表面平坦：粉碎層蝕刻........................41
4.2 實驗設備與分析儀器..................................42
五、實驗結果與討論......................................52
5.1 多晶矽沉積及蝕刻後狀況..............................52
5.2 SOI薄膜轉移後表面情形...............................52
5.3 SOI薄膜粉碎層蝕刻情形...............................54
六、結論................................................67
參考文獻................................................ 69

參考文獻

〔1〕吳憲昌，陳啟東，「單電子電晶體的進展與應用」，自然科學簡訊，第十五卷第四期，115-118頁，2003。
〔2〕 J. B. Lasky, et al., “Silicon-on-Insulator (SOI) by Bonding and Etch-Back”, Electron Devices Meeting, 1985 International, Vol. 31, pp. 684-687, 1985.
〔3〕 G. K. Celler and S. Cristoloveanu, “Frontiers of Silicon-on- Insulator”, Journal of Applied Physics, Vol. 93, Issue 9, pp. 4955-4978, May 2003.
〔4〕 H. Xiao著，半導體製程技術導論，羅正忠和張鼎張譯，二版，臺灣培生教育出版，臺北市，民國九十三年。
〔5〕莊達人，VLSI製造技術，五版，高立圖書有限公司，臺北縣，民國九十一年。
〔6〕 J. B. Kuo and K.-W. Su, CMOS VLSI Engineering: Silicon-on-Insulator (SOI), Kluwer Academic Publishers, Boston, 1998.
〔7〕陳威良，「電漿離子佈植製作SOI及佈植缺陷之研究」，國立清華大學，碩士論文，民國九十年。
〔8〕李隆盛，「非正統之金氧半導體場效電晶體」，電子與材料雜誌 14，80-85頁，2002。
〔9〕 J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 3rd Edition, Springer Science+Business Media, Inc., New York, 2004.
〔10〕G. L. Sun, et al., “Cool Plasma Activated Surface in Silicon Wafer Direct Bonding Technology”, Journal de Physique, Vol. 49, No. 9, pp. C4-79-C4-82, September 1988.
〔11〕Q.-Y. Tong and U. Gösele, Semiconductor Wafer Bonding: Science and Technology, John Wiley＆Sons, Inc., New York, 1999.
〔12〕T.-H. Lee, “Semiconductor Thin Film Transfer by Wafer Bonding and Advanced Ion Implantation Layer Splitting Technologies”, Duke University, Doctoral Dissertation, 1998.
〔13〕M. Burel, “Silicon on Insulator Material Technology”, Electronics Letters, Vol. 31, Issue 14, pp. 1201-1202, July 1995.
〔14〕M. Burel, United States Patent, Patent Number：5374564.
〔15〕C. Maleville and C. Mazuré, “Smart-Cut® Technology: from 300 mm Ultrathin SOI Production to Advanced Engineered Substrates”, Solid-State Electronics, Vol. 48, Issue 6, pp. 1055-1063, June 2004.
〔16〕T. Yonehara, K. Sakaguchi and N. Sato, “Epitaxial Layer Transfer by Bond and Etch Back of Porous Si”, Applied Physics Letters, Vol. 64, Issue 16, pp. 2108- 2110, April 1994.
〔17〕H. Habuka, et al., “Roughness of Silicon Surface Heated in Hydrogen Ambient”, Journal of The Electrochemical Society, Vol. 142, Issue 9, pp. 3092-3098, September 1995.
〔18〕T. Yonehara and K. Sakaguchi, “ELTRAN®; Novel SOI Wafer Technology”, JSAP International, No. 4, pp. 10-16, July 2001.
〔19〕S. S. Iyer and A. J. Auberton-Herv'e, Silicon Wafer Bonding Technology for VLSI and MEMS Applications, Inspec, London, 2002.
〔20〕N. Sato, T. Yonehara, “Hydrogen Annealed Silicon-on-Insulator”, Applied Physics Letters, Vol. 65, Issue 15, pp. 1924-1926, October 1994.
〔21〕W. P. Maszara, et al., “Quality of SOI Film after Surface Smoothing with Hydrogen Annealing, Touch-Polishing”, SOI Conference, 1997. Proceedings., 1997 IEEE International, pp. 130-131, October 1997.
〔22〕N. Sato, et al., “Suppression of Si Etching during Hydrogen Annealing of Silicon-on-Insulator”, SOI Conference, 1998. Proceedings., 1998 IEEE International, pp. 17-18, October 1998.
〔23〕王建榮、林必窕和林慶福，半導體平坦化CMP技術，二版，全華科技圖書股份有限公司，臺北市，民國八十九年。
〔24〕M. Kulawski, “Advanced CMP Processes for Special Substrates and for Device Manufacturing in MEMS Applications”, VTT Publications 611, 80 p.+ app. 60 p., Technical Research Centre of Finland, September 2006.
〔25〕J. T. Mooney, et al., “Silicon on Insulator (SOI) Wafer Polishing Using Magnetorheological Finishing (MRF) Technology”, Proceedings of The 2003 ASPE 18th Annual Meeting, Portland OR, October 2003.
〔26〕M. Tricard, et al., “Prime Silicon and Silicon-on-Insulator (SOI) Wafer Polishing with Magnetorheological Finishing (MRF)”, Proceedings of The 2003 ASME International Mechanical Engineering Congress & Exposition (IMECE), Washington DC, November 2003.
〔27〕M. Tricard, et al., “SOI Wafer Polishing with Magnetorheological Finishing (MRF)”, SOI Conference, 2003. IEEE International, pp. 127-129, September 2003.
〔28〕http://www.opticsexcellence.org/SJ_TeamSite/RS_mrf.html。
〔29〕http://www.atp.nist.gov/1999national/epion.pdf。
〔30〕N. Toyada, S. Matsui and I. Yamada, “Ultra-Smooth Surface Preparation Using Gas Cluster Ion Beams”, Japanese Journal of Applied Physics, Vol. 41, No. 6B, pp. 4287-4290, June 2002.
〔31〕L. P. Allen, et al., “SOI Uniformity and Surface Smoothness Improvement Using GCIB Processing”, SOI Conference, IEEE International 2002, pp. 192-193, October 2002.
〔32〕http://en.wikipedia.org/wiki/Gas_cluster_ion_beam。
〔33〕A. Thilderkvist, et al., “Surface Finishing of Cleaved SOI Films Using Epi Technologies”, SOI Conference, 2000 IEEE International, pp. 12-13, October 2000.
〔34〕S. G. Kang and I. J. Malik, United States Patent, Patent Number：6287941 B1.
〔35〕F. J. Henley, “Layer-Transfer Quality Cleave Principles”, The Silicon Genesis Corporation, July 2005.
〔36〕http://www.sigen.com/。
〔37〕http://web.mit.edu/6.774/www/handout_33.pdf。
〔38〕L. Scudder and A. Al-Bayati, “Selective Silicon Processing for Advanced Ultra Shallow Junction Engineering”, Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on, pp. 91-95, September 2002.
〔39〕邱文俊，「KOH/醇類蝕刻液系統應用於單晶矽濕式蝕刻之研究」，國立清華大學，博士論文，民國九十三年。
〔40〕http://www.me.ntou.edu.tw/~lyh/course/course03/docs/etching.pdf。
〔41〕H Seidel, et al., “Anisotropic Etching of Crystalline Silicon in Alkaline Solutions. I, Orientation Dependence and Behavior of Passivation Layers”, Journal of The Electrochemical Society, Vol.137, No. 11, pp. 3612-3626, November 1990.
〔42〕R. M. Finne and D. L. Klein, “A Water-Amine-Complexing Agent System for Etching Silicon”, Journal of The Electrochemical Society, Vol. 114, Issue 9, pp. 965-970, September 1967.
〔43〕P.-H. Chen, et al., “The Characteristic Behavior of TMAH Water Solution for Anisotropic Etching on Both Silicon Substrate and SiO2 Layer”, Sensors and Actuators A: Physical, Vol. 93, No. 2, pp. 132-137, September 2001.
〔44〕H. Wu, J.Cargo and M. White, “Characterization of Various Etching Techniques for Gate Level Failure Analysis and Substrate Decoration for Advanced Cu/low k Technologies”, Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the, pp. 242-248, Singapore, June 2005.
〔45〕V. S. Speriosu, B. M. Paine and M.-A. Nicolet, “X-Ray Rocking Curve Study of Si-Implanted GaAs, Si and Ge”, Applied Physics Letters, Vol. 40, Issue 7, pp. 604-606, April 1982.
〔46〕K. R. Williams, K. Gupta and M. Wasilik, “Etch Rates for Micromachining Processing-Part II”, Microelectromechanical Systems, Journal of, Vol. 12, Issue 6, pp. 761-778, December 2003.
〔47〕http://203.64.230.25/EM_folder/931215fareast3.pdf。
〔48〕小川洋輝，崛池靖浩著，半導體潔淨技術，顏誠廷譯，普林斯頓國際有限公司，臺北縣，民國九十二年。
〔49〕M. Bruel, B. Aspar and A. J. Auberton-Hervé, “Smart-Cut: A New Silicon on Insulator Material Technology Based on Hydrogen Implantation and Wafer Bonding”, Japanese Journal of Applied Physics, Vol. 36, No. 3B, pp. 1636- 1641, March 1997.
〔50〕C. Malleville, et al., “Wafer Bonding and H-Implantation Mechanisms Involved in The Smart-Cut Technology”, Material Science and Engineering B, Vol. 16, pp. 14-19, 1997.

指導教授

李天錫(Tien-Hsi Lee)

審核日期

2007-7-12

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