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姓名 陳政欣(Cheng-hsin Chen) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 矽基板氮化鎵電晶體閘極佈局研究
(The study of layout design in GaN HEMTs on Si substrate)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 本論文主要針對在低阻值矽(111)基板上進行氮化鋁鎵/氮化鎵電晶體製作與研究,並使用新的閘極佈局方式來提升汲極電流,以降低晶片成本。而電晶體製作採用離子佈植(Ion Implant)作為元件隔絕。
論文中,當元件的汲極到源極距離為9 µm,閘極長度為2 µm寬度為104 µm的元件上,單閘極佈局元件的特性為IDSS = 762.7mA/mm, VTH = -7.4 V,而矩陣型佈局元件可以比單閘極佈局元件在相同的元件主動區面積下,得到汲極電流的提升,大約87%的增加量。若在導通電流同約為140 mA時,矩陣型佈局元件可以比單閘極佈局元件在元件主動區結節省約45%的面積。最後,深入探討單閘極元件與矩陣型布局元件間電容與熱阻特性之變化。摘要(英) Two kinds of AlGaN/GaN HEMTs with different device layouts were fabricated and compared. A new matrix layout is proposed to reduce device active area while keeping drain current capability. Compared to device with single finger layout and similar drain current (IDSS = 140 mA), device with matrix layout saves 45% active area. When both of them have the same active area, device with new matrix layout can achieve 1.87 times higher IDSS than device with single finger layout. Finally, the gate capacitances and the thermal resistance of devices with new matrix layout and single finger layout are discussed. 關鍵字(中) ★ 元件佈局
★ 氮化鎵關鍵字(英) ★ device layout
★ GaN論文目次 摘要 I
ABSTRACT II
致謝 III
圖目錄 V
表目錄 VIII
第一章 緒論 1
1.1前言 1
1.2矽基板氮化鎵高電子遷移率場效電晶體之發展與相關佈局研究 3
1.3本論文研究動機與目的 7
1.4論文架構 8
第二章 氮化鋁鎵/氮化鎵場效電晶體於矽基板電晶體之與製程與特性分析 9
2.1前言 9
2.2氮化鋁鎵/氮化鎵成長於矽基板之磊晶結構 9
2.3蕭特基閘極場效電晶體製作與絕緣特性分析 13
2.3.1蕭特基閘極場效電晶體製作流程 13
2.3.2離子佈植原理與元件隔絕性分析 16
2.4電晶體閘極佈局設計與元件特性模擬 24
2.5 結論 29
第三章 氮化鋁鎵/氮化鎵場效電晶體佈局之特性分析 30
3.1前言 30
3.2不同佈局之元件直流特性分析 30
3.2.1類似汲極電流,不同元件佈局研究 30
3.2.2 相同元件主動區面積,不同佈局元件研究 34
3.3不同佈局之元件熱阻特性比較 41
3.4不同佈局之元件電容特性 46
3.5 不同佈局之元件動態電阻變化 49
3.6結論 53
第四章 結論 55
參考文獻 56
附錄Ⅰ 蕭特基閘極場效電晶體製作流程 58參考文獻 [1] L. F. Eastman and U. K. Mishra, “The toughest transistor yet GaN transistors,” in IEEE Spectrum, California, vol. 3, pp.28-33, May 2002
[2] K.S. Boutros, S. Burnham, D. Wong, K. Shinohara et al, “Normally-off 5A/1100V GaN-on-Silicon Device for High Voltage Applications” in IEEE International Electron Devices Meeting (IEDM), 2009, pp. 1-3
[3] Beach Robert,“III-nitride device with improved layout geometry” U.S. Patent 7417257, Aug 26, 2008
[4] Tiemeijer Lukas Frederik, “High frequency transistor layout for low source drain capacitance” U.S. Patent 7265399,Sep 04, 2007
[5] Geoff Haynes, “State of the art GaN switches and their relevance to SMART DC in the UK,” GaN Systems Inc. 2012
[6] D. Balaz, “Current Collapse and Device Degradation in AlGaN/GaN Heterostructure Field Effect Transistors” Ph.D. thesis, Dept. Elect. Eng, Glasgow Univ, Glasgow, UK, 2010.
[7] Y. C. Kong, Y.D. Zheng, C. H. Zhou, S.L. Gu, R. Zhang, P. han, Y. Shi, R. l. Jiang, “ Two-dimensional electron gas densities in AlGaN/AlN/GaN heterostructures,” in Appl. Phys. A 84, pp. 95–98, 2006
[8] GaN HEMT Technology ,Wayne Johnson and Edwin L. Piner, Kopin Co.,2011, pp 209-237
[9] T. E. Seidel, “Ion Implantation.” in S. M. Sze, Ed., VLSI Technology, McGraw-Hill, New York, 1983.
[10] I. Brodie and J. J. Muray, “The Physics of Microfabrication, Plenum”, New York, 1982.
[11] 薛光博, “砷化鎵場效電晶體表面氧離子佈植和自我校準技術之研究,”碩士論文,國立中央大學, 中壢, 台灣, 2001.
[12] S. M. Sze, “Semiconductor Devices: Physics and Technology,” Chap. 10, John Wiley & Sons, 1985.
[13] M. T. Robinson, and O. S. Oen, “The effect of channeling on displacement cascade theory” in Applied Physics Letter, vil. 2, pp. 30, 1963.
[14] Jungwoo Joh and Uttiya Chowdhury “Method for Estimation of the Channel Temperature of GaN High Electron Mobility Transistors” in ROCS Workshop, 2007.[Reliability of Compound Semiconductors Digest], pp. 87-89,Oct. 2007指導教授 辛裕明(Yue-ming Hsin) 審核日期 2014-8-19 推文 plurk
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