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姓名	洪政亮(Cheng-Liang Hung)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	高速有線傳輸系統之時脈產生器關鍵技術 (On Techniques of Clock Generator Used in High-Speed Wireline Transmission Systems)
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摘要(中)	隨著積體電路製造技術促進高速數據傳輸的發展，資料傳輸量發展至每秒數兆位元(Gb/s)。高速串列連結技術(high-speed serial link technology)是現今主要數據傳輸技術，亦被廣泛應用在有線收發裝置上。然而，在整個高速串列連結系統中，其性能關鍵取決於時脈產生器(timing clock generator)的品質和精準度。因此，鎖相迴路(phase-locked loop, PLL)或展頻時脈產生器(spread-spectrum clock generator, SSCG)在關鍵時脈產生器扮演重要的角色。 當資料傳輸速率已達每秒數兆位元，發射端的傳輸資料往往伴隨高次諧波，這將導致電磁干擾(electromagnetic interference, EMI)，並且嚴重影響周遭其他裝置。為了解決此問題，本論文提出了一在90 nm CMOS製程使用分數型鎖相迴路具三角波調變之6-GHz展頻時脈產生器。本論文提出的相位旋轉技術，乃透過調變分數除率來實現展頻時脈(spread-spectrum clocking, SSC)，此技術有效補償瞬時時序錯誤，同時避免量化誤差的產生。與傳統展頻時脈產生器使用三角積分調變相比，傳統展頻時脈產生器改變多模數除率造成蓄意的相位跳動等效分數除率，本論文實現無擾動真實性分數除率。量測結果顯示本方法抑制方均根抖動量小於1 ps，因此在抖動性能上具有顯著改善。 此外，目前有線收發技術應用須具備向下相容能力，使得資料傳輸速率涵蓋了數Gb/s範圍，這也驅使設計一具寬範圍時脈產生器可支援數種世代規格。因此，時脈產生器中的壓控震盪器(voltage-controlled oscillator, VCO)扮演關鍵的角色。本論文提出了一在90 nm CMOS製程使用主動電感之寬頻率調諧範圍LC-壓控震盪器，此LC-壓控制震盪器在有線收發機介面相容性設計上，更具彈性及無須重新設計之特點。其可操作頻率範圍使得時脈產生器得以應用數種不同規格。另外本論文所提出主動電感亦顯示降低電感損耗特性來提升其品質因素(quality factor, Q)。量測0.9至8 GHz調諧範圍(160%)之間的相位雜訊在中心頻率偏移1 MHz為–118至–105 dBc/Hz。 時脈產生器中另一重要電路為除頻器(frequency divider, FD)，意味除頻器必須能在最高時脈頻率下處理除頻訊號。因此本論文提出了一在90 nm CMOS製程具高速操作且具備混合模數之可編程化除頻器，藉由提出一具三模式模數切換的除法器單元，使用於現有的多模除頻器(multi-modulus divider, MMD)，可實現1步階或0.5步階模數的改變，亦顯示運用於三角積分調變時，將具備抑制–6 dB量化雜訊之優點。此外，本論文在除頻器單元中的數位邏輯電路使用主動電感與一自我省電技巧，使除頻器具高速功能、全數位操作及良好功率效率表現。量測操作在輸入頻率6.25 GHz時，除頻器的功率效率為2.12 GHz/mW。 最後，本論文整合所提之技術，實現另一5 GHz展頻時脈產生器。同時，在模擬USB 3.1 10 Gb/s測試環境下利用USB 3.1規範的一致性測試，進行展頻時脈產生器的抖動量測。綜觀本論文所提技術顯示，本論文所提出的架構可因應未來下一世代高速有線收發機介面。
摘要(英)	Advance in integrated circuit (IC) fabrication technology facilitates the high-speed transmission of data to be upward evolved into several gigabits per second (Gb/s). The high-speed serial link technology is the major technique in modern data transmission. It is widely employed in wireline SerDes applications. In the overall high-speed serial link systems, however, the performance depends crucially on the quality and precision of the essential timing clock generator. Thus, a phase-locked loop (PLL) or a spread-spectrum clock generator (SSCG) plays an important role in such critical building block for clock generation. As the transmitted data rate has been upgraded into milti-Gb/s, the signal of the data launched by the transmitter (TX) accompanies the higher order harmonics. It results in the power-radiated electromagnetic interference (EMI) issue and may stringently affect the other equipment in the vicinity. To address this issue, this dissertation presents a 6-GHz triangular-modulated SSCG based on a fractional-N PLL in a 90-nm CMOS process. The proposed phase-rotating technique implements the spread-spectrum clocking (SSC) by modulating the fractional-N ratios. The presented technique effectively compensates the instantaneous timing error and shows the ignorable quantization error. Unlike the delta-sigma (ΔΣ) technique commonly used for SSCGs, the proposed SSCG realizes non- dithered fractional division ratios. It shows that the deliberate phase jump stemming from the ΔΣ control could be dismissed. In terms of SSC, this approach suppresses the RMS jitter to be less than 1 ps, showing a significant improvement in the jitter performance. In the current wireline SerDes application, it evolves the coexistence of several specification generations, and covers the data rate range of several Gb/s. As a result, a wide range clock generator to support multi-specification generations is desirable, and thus, the sub-building block of the clock generator, i.e., the voltage-controlled oscillator (VCO), plays the critical role. This dissertation presents a wide frequency tuning range inductor- capacitor-based VCO (LC-VCO) with an active inductor in a 90-nm CMOS process. The proposed LC-VCO is intended to be flexible without redesign for several new-generation wireline SerDes interfaces. The wide operating frequency makes the clock generator applicable to the multistandards. As a result, the proposed active inductor shows a quality factor, i.e., Q, enhancement technique for the reduction in the loss from the active inductor, deriving an appropriate phase noise of –105 to –118 dBc/Hz at a 1-MHz offset over the entire tuning range of 0.9 to 8 GHz (160%). In addition, the other essential sub-building block is the frequency divider (FD). It implies that the FD must process the signal operating at the highest clock frequency. Thus, this dissertation presents a high-speed power-efficient programmable frequency divider with a hybrid integer/fraction modulus steps in a 90-nm CMOS. Based on the proposed divider cell used in the multi-modulus divider (MMD), the FD easily realizes the flexible modulus 1- or 0.5-step-size MMD, showing the potential merit of the –6-dB suppressed quantization noise. In addition, by the embodiment of active-inductor-based digital logic cells with a self-power-saving scheme in the divider, the capabilities of high-speed, all-digital operation and good power-efficient are derived. Operating at 6.35 GHz, the perfectible power efficiency is 2.12 GHz/mW. As a result, integrating the advanced technique that presented, the dissertation also presents a 5-GHz, dual SSC mechanism SSCG. Meanwhile, a similar USB 3.1 10 Gb/s compliance test is set up for the demonstration of the SSCG jitter measurement. Such work might be appropriate for the new-generation of the high-speed wireline SerDes interfaces.
關鍵字(中)	★ 有線收發機介面 ★ 展頻時脈產生器 ★ 分數型鎖相迴路 ★ 相位補償式分數除頻器 ★ 差動主動式電感 ★ 壓控震盪器 ★ 寬頻 ★ 多模數除頻器	關鍵字(英)	★ wireline SerDes interfaces ★ spread-spectrum clock generator ★ fractional-N phase-locked loop ★ phase-compensated fractional divider ★ differential active inductor ★ voltage-controlled oscillator ★ wideband ★ multi-modulus divider
論文目次	摘要 i Abstract iii Acknowledgements vi Table of Contents ix Figure Captions xiii Table Captions xviii Chapter 1 Introduction 1 1.1 Evolution of High-Speed Serial Link Typology 1 1.2 Motivation 3 1.2.1 FORWARDED CLOCK ARCHITECTURE 3 1.2.2 EMBEDDED CLOCK ARCHITECTURE 3 1.2.3 MOTIVATION IN THE DESIGN OF CRITICAL BUILDING BLOCK IN HIGH-SPEED SERIAL LINK SYSTEM 4 1.3 Thesis Organization 6 Chapter 2 The Fundamental of the Critical Building Block in the High-Speed Serial Link System 9 2.1 Electromagnetic Interference 9 2.1.1 EFFECTS OF ELECTROMAGNETIC FIELD 9 2.1.2 INHERENT DIFFERENTIAL SIGNALING FOR EMI REDUCTION 10 2.2 Overview of Spread-Spectrum Clock Generators 11 2.2.1 DIRECT VCO MODULATION SSCG 12 2.2.2 OPEN-LOOP MULTIPHASE VCO SSCG 13 2.2.3 DELTA-SIGMA MODULATION SSCG 14 2.2.3.1 CONVENTIONAL ΔΣ-BASED FRACTIONAL-N PLL FOR SSCG 14 2.2.3.2 TIMING IMPACT OF ΔΣ-BASED SSCG 15 2.2.3.3 CLOSED-LOOP MULTIPHASE VCO SSCG 16 2.2.3.4 PULSE-SWALLOW FRACTIONAL DIVIDER SSCG 17 2.2.3.5 MULTIPHASE FRACTIONAL DIVIDER SSCG 18 2.2.3.6 DIGITAL DELAY LINE FRACTIONAL DIVIDER SSCG 19 2.2.4 ALL DIGITAL SSCG 21 2.2.4.1 ALL DIGITAL ΔΣ-FREE UNDER-DAMPING SSCG 22 2.2.5 SELF-OSCILLATING NATURE FREQUENCY SSCG 24 2.2.6 CHAOTIC PULSE-AMPLITUDE MODULATION SSCG 25 2.2.7 SUMMARY 28 Chapter 3 A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique 29 3.1 SSCG Architecture 29 3.1.1 OVERVIEW OF STATE-OF-THE-ART PHASE-COMPENSATION-RELATED APPROACHES 29 3.1.2 SYSTEM ARCHITECTURE OF PROPOSED SSCG 31 3.1.3 PHASE-COMPENSATED FRACTIONAL DIVIDER 34 3.2 Linear Analysis of Proposed SSCG 40 3.2.1 LINEAR MODEL ANALYSIS 40 3.2.2 TRIANGULAR-MODULATED WAVEFORM FOR DOWN-SPREADING SPECTRUM CLOCKING 43 3.2.3 EFFECT OF INTERPOLATED PHASE MISMATCH ON PROPOSED SSCG 45 3.3 Circuit Implementation 50 3.3.1 LC-VCO 50 3.3.2 DIVIDE-BY-119/120 DUAL-MODULUS DIVIDER 50 3.3.3 PHASE BLENDER 52 3.3.4 CURRENT SEGMENT AND PHASE INTERPOLATOR 53 3.3.5 MODULATION PROFILE 57 3.3.6 CHARGE PUMP AND LOW-PASS FILTER 57 3.4 Experimental Results 59 Chapter 4 A 0.9–8 GHz VCO with a Differential Active Inductor for Multistandard Wireline SerDes 65 4.1 Background 65 4.1.1 TREND OF HIGH-SPEED SERIAL-LINK-BASED WIRELINE COMMUNICATIONS 65 4.1.2 DILEMMA OF PRIOR WORKS FOR VCO 66 4.2 Circuit Description 67 4.2.1 LC-VCO CIRCUIT TOPOLOGY 67 4.2.2 SELF-CALIBRATION TECHNIQUE 69 4.2.3 PROPOSED DIFFERENTIAL ACTIVE INDUCTOR 72 4.2.3.1 ARCHITECTURE 72 4.2.3.2 SMALL-SIGNAL ANALYSIS 73 4.2.3.3 SIMULATION OF DIFFERENTIAL ACTIVE INDUCTOR 75 4.2.4 DESIGN CONSIDERATIONS 77 4.2.4.1 EFFECT OF ACTIVE-INDUCTOR-BASED LC-VCO 77 4.2.4.2 TUNING CURVE DRIFTING OF SELF-CALIBRATION TECHNIQUE 78 4.2.4.3 PHASE NOISE ESTIMATION 79 4.3 Experimental Results 81 Chapter 5 A 6.35-GHz, 2.12-GHz/mW 1/0.5-Modulus-Step Frequency Divider With a Hybrid Modulus-Switching Divider Cell Using a Self-Power-Saving Scheme 87 5.1 Background 87 5.1.1 ESSENTIAL BUILDING BLOCK OF SSCG 87 5.1.2 FUNCTIONS OF DESIRED FREQUENCY DIVIDER 88 5.2 Circuit Description 88 5.2.1 HYBRID MMD CIRCUIT TOPOLOGY 88 5.2.2 TRIPLE DIVIDE-BY-1/1.5, -2/1, -2/3 DIVIDER CELL 92 5.2.2.1 DIVIDE-BY-1/1.5 DIVIDER CELL 93 5.2.2.2 DIVIDE-BY-2/1 DIVIDER CELL 95 5.2.2.3 DIVIDE-BY-2/3 DIVIDER CELL 96 5.2.3 DESIGN CONSIDERATIONS FOR TRIPLE-MODULUS DIVIDER CELL 98 5.2.3.1 TIMING ISSUE 98 5.2.3.2 INPUTS FOR DOUBLE-EDGE-TRIGGERED DFF 99 5.2.4 ACTIVE-INDUCTOR-BASED DIGITAL LOGICS WITH SELF-POWER-SAVING SCHEME 99 5.2.4.1 BANDWIDTH EXTENSION TECHNIQUE FOR ACTIVE-INDUCTOR-BASED DIGITAL LOGICS 103 5.2.5 SIMULATION RESULTS 106 5.2.5.1 COMPARISON W/ & WO/ ACTIVE INDUCTOR LOADING FOR DIGITAL LOGIC CELL 106 5.2.5.2 COMPARISON BETWEEN DIFFERENT ARCHITECTURES OF LATCH FOR MMD 108 5.2.6 DESIGN CONSIDERATIONS FOR ACTIVE-INDUCTOR-BASED MMD 110 5.3 Experimental Results 111 5.3.1 DIVISION RATIOS MEASUREMENT 112 5.3.2 PHASE NOISE OF HYBRID MMD 116 5.3.3 INSTANTANEOUS FREQUENCY FLUCTUATION OF SSCG 117 Chapter 6 SSCG Jitter Measurement by Compliance Test to Similar USB 3.1 10 Gb/s 121 6.1 Dual SSC Mechanism SSCG 121 6.2 Measurement Environment 125 6.2.1 USB 3.1 TX NORMATIVE SETUP FOR COMPLIANCE TEST 125 6.2.2 SSC JITTER BY USB 3.1 TX COMPLIANCE TEST 125 6.3 Experimental Results 130 Chapter 7 Conclusions and Future Works 135 7.1 Conclusions 135 7.2 Future Works 137 References 139 Publication List 145
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指導教授	鄭國興(Kuo-Hsing Cheng)	審核日期	2014-11-27
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