博碩士論文 955201027 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:30 、訪客IP:18.221.23.0
姓名 侯致聖(Chih-Sheng Hou)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於系統晶片隨機存取記憶體之自我修復技術與規劃架構
(Built-in self-repair technique and planning framework for RAMs in SoCs)
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摘要(中) 先進系統晶片(SoC)具有上百個以具侵略性的隨機存取記憶體(random access memory),然而這些隨機存取記憶體通常佔據著絕大部分矽晶片的面積,也因此系統晶片中內嵌式(embedded)記憶體的良率(yield)嚴重地影響系統晶片的良率,有效的記憶體良率提升技術是相當重要。內建自我修復電路(built-in self-repair, BISR) 廣泛地使用於系統晶片內記憶體之修復。由於大量的記憶體存在於系統晶片之中,如何有效地提升記憶體修復效率、降低測試暨修復時間、以及縮小內建自我修復電路之硬體成本皆是相當重要的議題。
在論文中第一部分提出一個高修復效率之記憶體內建自我修復界面(high-repair-efficiency BISR, HRE-BISR),藉由重覆使用一個區域型的位元地圖(local bitmap)在正常操作模式下(normal mode)達成修復元件之功能以此方式修復更多記憶體內部之瑕疵。首先我們提出一個重覆使用區域型位元地圖達成備份位元之記憶體內建自我修復界面(HRE-BISR-SB),搭配著一個行/列/位元之備份元件分析演算法(row/column/bit redundancy analysis algorithm)配置其內部汁備份元件。模擬結果顯示相較於傳統內建自我修復電路在各種不同的錯誤分布情況下(fault distribution),其HRE-BISR-SB介面可額外提升0.48%~11.95%的修復效率,另一方面,一個重覆使用區域型位元地圖達成備份字組(word)之記憶體內建自我修復界面(HRE-BISR-SW),相較於無重複使用技術的內建自我修復界面,其HRE-BISR-SW介面可額外提升0.71%~5.55%的修復效率。為了能夠有效地尋找最佳的備份元件配置的方式,因此提出一個最小備份元件尋找演算法以此搜尋最小硬體成本的配置方案。
在論文中第二部分提出一個以修復效率為基準的記憶體測試排程技術,藉此方式在一個限定測試功率之情況下縮短具有內建自我修復電路之記憶體的測試暨修復時間。因此,根據其修復效率所計算出之提早中止機率(early abort probability),我們提出高效率測試排程演算法來達成上述目標。實驗結果顯示,所提出的高效率測試排程演算法可以縮短記憶體測試暨修復時間,以ITC’02實驗樣本(ITC’02 benchmark)為例子,相較於現存的記憶體排程演算法,本演算法可以平均降低10.7%之預估測試暨修復時間。
在論文中第三部分提出一個運用分享式記憶體內建自我修復電路於系統晶片中記液體內建自我修復電路規劃企劃(memory BISR planning framework, MBiP),首先,在MBiP中具有記憶體群組化演算法(memory grouping algorithm)來達到挑選記憶體共享一個分享式記憶體內建自我修復電路。緊接著,依據測試排程演算法與記憶體群組演算法之結果,記憶體內建自我修復電路配置演算法(BISR scheme allocation algorithm)用於配置不同型態的分享式記憶體自我修復電路。實驗結果顯示,相較於獨立式記憶體內建自我修復電路(dedicated BISR),針對50個記憶體在350mW測試功率與1.5mm繞線距離之限制情況下,藉由MBiP配置記憶體內建自我修復電路的硬體成本可以減少22%。最後,考量存在著不同前建結測試(pre-bond test)與後建結測試(post-bond test)下的測試功率,MBiP拓展至規畫記憶體內建自我修復電路於三維積體電路內系統晶片之記憶體。實驗結果顯示,相較於獨立式記憶體內建自我修復電路(dedicated BISR),在500mW前建結測試功率、600mW後建結測試功率與1mm繞線距離之限制情況下,藉由MBiP配置記憶體內建自我修復電路的硬體成本可以減少35%。
摘要(英) Modern system-on-chips (SoCs) typically encompass several hundreds of random access memory
(RAM) cores designed with aggressive design rules. Those memory cores usually represent
a significant portion of the chip area. Therefore, the yield of memory cores has heavy
impact on the SoC yield. Effective yield-enhancement techniques for those memory cores
thus are imperative. Built-in self-repair (BISR) technique has been widely used to repair
the memory cores in SoCs. Since a large amount of RAMs are distributed in a SoC, how to
boost the repair efficiency, minimize test and repair time, and minimize area cost of BISR
circuits is an important issue.
In the first part of this thesis, a high-repair-efficiency BISR scheme (HRE-BISR) is proposed.
The HRE-BISR reuses a local bitmap to serve as redundancy elements in normal mode
such that it can repair more faults. First, a HRE-BISR scheme reusing the local bitmap as
spare bits (HRE-BISR-SB) is presented. In addition, a row/column/bit redundancy analysis
algorithm is proposed to allocate redundancies of a RAM with the HRE-BISR-SB scheme.
Simulation results show that the proposed HRE-BISR-SB scheme can provide 0.48%–11.95%
increment of repair rate than a typical BISR scheme without reusing the local bitmap as
spare bits for different fault distributions. Secondly, a HRE-BISR scheme reusing the local
bitmap as spare words (HRE-BISR-SW) is presented, which can provide 0.71%–5.55% increment
of repair rate than a BISR scheme without reusing the local bitmap as spare words.
Finally, a minimal redundancy configuration searching algorithm is proposed to find a redundancy
configuration with minimal area cost for a RAM with HRE-BISR scheme under
a targeted repair rate.
In the second part of this thesis, a repair-rate-driven test scheduling technique is proposed
to minimize the test and repair time of RAMs with BISR circuits under the constraint of
maximum power consumption. An efficient test scheduling algorithm based on the earlyabort
probability calculated according to the repair rate is proposed. Simulation results show
that the proposed algorithm can achieve smaller test and repair time than existing works.
For ITC’02 benchmarks, for example, about 10.7% average reduction of expected test and
repair time can be achieved by the proposed algorithm.
In the third part of this thesis, a memory BISR planning (MBiP) framework is proposed
to plan shared BISR schemes for the RAMs in a SoC. The MBiP framework consists of a
memory grouping algorithm to select RAMs which can served by a shared BISR circuit.
Then, a BISR scheme allocation algorithm is proposed to allocate different shared BISR
schemes for the RAMs under the constraints of the results of memory grouping and a test
scheduling. Simulation results show that, about 22% area reduction can be achieved by
the proposed MBiP framework for 50 RAMs under 1.5mm distance constraint and 350mW
test power constraint in comparison with a dedicated BISR scheme. Finally, we extend the
MBiP framework to support the planning of shared BISR schemes for RAMs in SoC dies of
three-dimensional ICs by considering the constraints of pre-bond and post-bond test power
constraints. Simulation results show that 35% area reduction can be achieved by the shared
BISR scheme planned by the proposed planning technique under 1mm distance constraint,
500mW pre-bond test power, and 600mW post-bond test power constraints in comparison
with a dedicated BISR scheme.
關鍵字(中) ★ 記憶體
★ 隨機存取記憶體
★ 內建自我修復電路
關鍵字(英) ★ memory
★ RAM
★ BISR
論文目次 1 Introduction 1
1.1 Why BISR is Needed for Embedded memories . . . . . . . . . . . . . . . . . 1
1.2 Typical BISR Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Existing BISR Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3.1 Redundancy Analysis Algorithm . . . . . . . . . . . . . . . . . . . . . 3
1.3.2 BISR Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Challenges of BISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Thesis Scope and Contribution . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 High Repair Efficiency BISR Schemes 13
2.1 Concept of Reusing BIRA for Spare Elements . . . . . . . . . . . . . . . . . 13
2.2 HRE-BISR Scheme Reusing Bitmap as Spare Bits . . . . . . . . . . . . . . . 18
2.2.1 Proposed BISR Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.2 Proposed RCB-RA Algorithm . . . . . . . . . . . . . . . . . . . . . . 22
2.2.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3 HRE-BISR Scheme Reusing Bitmap as Spare Words . . . . . . . . . . . . . . 31
2.3.1 Proposed BISR Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3.2 Proposed CRESTA-SW Algorithm . . . . . . . . . . . . . . . . . . . 37
2.3.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4 Minimal Redundancy Finding for RAMs with HRE-BISR Scheme . . . . . . 43
2.4.1 Redundancy Configuration Decision Flow . . . . . . . . . . . . . . . . 44
2.4.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3 Repair-Rate-Driven Test Scheduling for BISRed RAMs 57
3.1 Test and Repair Time Reduction of BISRed RAMs . . . . . . . . . . . . . . 57
3.2 Typical Memory BISR Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3 Memory Test Scheduling Problem Formulation . . . . . . . . . . . . . . . . . 60
3.4 Proposed Test Scheduling Algorithm . . . . . . . . . . . . . . . . . . . . . . 62
3.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4 Memory BISR Planning Framework for RAMs in SoCs 68
4.1 Test Time and Area Reduction of BISRed RAMs . . . . . . . . . . . . . . . 68
4.2 Proposed MBiP Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.2.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3 Proposed Memory Grouping Technique . . . . . . . . . . . . . . . . . . . . . 76
4.3.1 Memory Grouping Algorithm . . . . . . . . . . . . . . . . . . . . . . 76
4.3.2 Valid Grouping Generation . . . . . . . . . . . . . . . . . . . . . . . . 78
4.3.3 Seed Solution Generation . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.3.4 Better Solution Generation Using Seed Proliferation . . . . . . . . . . 79
4.4 Redundancy Configuration Simulation . . . . . . . . . . . . . . . . . . . . . 82
4.4.1 High Yield Improvement and Low Cost Impact RAM Selection Algorithm 84
4.4.2 HRE-BISR Scheme Replacement . . . . . . . . . . . . . . . . . . . . 84
4.4.3 Redundancy Complexity Reduction . . . . . . . . . . . . . . . . . . . 87
4.5 Proposed Shared BISR Allocation Technique . . . . . . . . . . . . . . . . . . 87
4.6 Simulation and Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5 MBiP Framework for RAMs in SoC Dies of 3D ICs 104
5.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2 Proposed Memory BISR Allocation Scheme . . . . . . . . . . . . . . . . . . 106
5.2.1 Test Resource Compatible Table Generation . . . . . . . . . . . . . . 107
5.2.2 BISR-Circuit Minimization Algorithm . . . . . . . . . . . . . . . . . 109
5.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6 Conclusion and Future Work 117
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
參考文獻 [1] Y. Zorian, “Embedded memory test & repair: Infrastructure IP for SOC yield,” in Proc. Int’l
Test Conf. (ITC), Baltmore, Oct. 2002, pp. 340–349.
[2] I. Kim, Y. Zorian, G. Komoriya, H. Pham, F. P. Higgins, and J. L. Lweandowski, “Built in
self repair for embedded high density SRAM,” in Proc. Int’l Test Conf. (ITC), Oct. 1998, pp.
1112–1119.
[3] Y. Zorian and S. Shoukourian, “Embedded-memory test and repair: Infrastructure IP for SoC
yield,” IEEE Design & Test of Computers, vol. 20, pp. 58–66, May-June 2003.
[4] V. Schober, S. Paul, and O. Picot, “Memory built-in self-repair using redundant words,” in
Proc. Int’l Test Conf. (ITC), Baltimore, Oct. 2001, pp. 995–1001.
[5] S. Nakahara, K. Higeta, M. Kohno, T. Kawamura, and K. Kakitani, “Built-in self-test for GHz
embedded SRAMs using flexible pattern generator and new repair algorithm,” in Proc. Int’l
Test Conf. (ITC), 1999, pp. 301–310.
[6] D. K. Bhavsar, “An algorithm for row-column self-repair of RAMs and its implementation in
the Alpha 21264,” in Proc. Int’l Test Conf. (ITC), Atlantic City, Sept. 1999, pp. 311–318.
[7] M. Nicolaidis, N. Achouri, and S. Boutobza, “Dynamic data-bit memory built-in self-repair,”
in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2003,
pp. 588–594.
[8] C.-L. Su, R.-F. Huang, and C.-W.Wu, “A processor-based built-in self-repair design for embedded
memories,” in Proc. 12th IEEE Asian Test Symp. (ATS), Xian, Nov. 2003, pp. 366–371.
[9] R. C. Aitken, “Applying defect-based test to embedded memories in a COT model,” in Proc.
IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), San Jose, July
2003, pp. 72–77.
[10] M. Nicolaidis, N. Achouri, and L. Anghel, “A diversified memory built-in self-repair approach
for nanotechnologies,” in Proc. IEEE VLSI Test Symp. (VTS), Napa Valley, Apr. 2004, pp.
313–318.
[11] C.-L. Su, Y.-T. Yeh, and C.-W. Wu, “An integrated ECC and redundancy repair scheme for
memory reliability enhancement,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance
in VLSI Systems (DFT), Monterey, CA, Oct. 2005, pp. 81–89.
[12] J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, “A built-in self-repair design for RAMs with
2-D redundancies,” IEEE Trans. on VLSI Systems, vol. 13, no. 6, pp. 742–745, June 2005.
[13] T.-W. Tseng, C.-H. Wu, Y.-J. Huang, J.-F. Li, A. Pao, K. Chiu, and E. Chen, “A built-in
self-repair scheme for multiport RAMs,” in Proc. IEEE VLSI Test Symp. (VTS), May 2007,
pp. 355–360.
[14] C.-D. Huang, J.-F. Li, and T.-W. Tseng, “ProTaR: and infrastructure IP for repairing RAMs
in SOCs,” IEEE Trans. on VLSI Systems, vol. 15, no. 10, pp. 1135–1143, Oct. 2007.
[15] T.-W. Tseng, J.-F. Li, and C.-C. Hsu, “ReBISR: a reconfigurable built-in self-repair scheme for
random access memories in SoCs,” IEEE Trans. on VLSI Systems, vol. 18, no. 6, pp. 921–932,
June 2010.
[16] T.-W. Tseng, Y.-J. Huang, and J.-F. Li, “DABISR: a defect-aware built-in self-repair scheme
for single/multi-port RAMs in SoCs,” IEEE Trans. on Computer-Aided Design of Integrated
Circuits and Systems, vol. 29, no. 10, pp. 1628–1639, Oct. 2010.
[17] J.-F. Li, T.-W. Tseng, and C.-S. Hou, “Reliability-enhancement and self-repair schemes for
SRAMs with static and dynamic faults,” IEEE Trans. on VLSI Systems, vol. 18, no. 9, pp.
1361–1366, Sept. 2010.
[18] T.-W. Tseng, J.-F. Li, and C.-S. Hou, “A built-in method to repair SoC RAMs in parallel,”
IEEE Design & Test of Computers, vol. 27, no. 6, pp. 46–57, Nov.-Dec. 2010.
[19] A. Tanabe, T. Takeshima, H. Koike, Y. Aimoto, M. Takada, T. Ishijima, N. Kasai, H. Hada,
K. Shibahara, T. Kunio, T. Tanigawa, T. Saeki, M. Sakao, H. Miyamoto, H. Nozue, S. Ohya,
T. Murotani, K. Koyama, and T. Okuda, “A 30-ns 64-Mb DRAM with built-in self-test and
self-repair function,” IEEE Jour. of Solid-State Circuits, vol. 27, no. 11, pp. 1525–1533, Nov.
1992.
[20] V. Schober, S. Paul, and O. Picot, “Memory built-in self-repair using redundant words,” in
Proc. Int’l Test Conf. (ITC), Oct. 2001, pp. 995–1001.
[21] D. Anand, B. Cowan, O. Farnsworth, P. Jakobsen, S. Oakland, M. R. Ouellette, and D. L.
Wheater, “An on-chip self-repair calculation and fusing methodology,” IEEE Design & Test
of Computers, vol. 20, no. 5, pp. 67–75, Sept. 2003.
[22] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Bulit-in redundancy analysis for memory
yield improvement,” IEEE Trans. on Reliability, vol. 52, no. 4, pp. 386–399, Dec. 2003.
[23] I. Kang, W. Jeong, and S. Kang, “High-efficiency memory BISR with two serial RA stages
using spare memories,” Electronics Letters, vol. 44, no. 8, pp. 515–516, Apr. 2008.
[24] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self-repair
analyzer (CRESTA) for embedded DRAMs,” in Proc. Int’l Test Conf. (ITC), Oct. 2000, pp.
567–574.
[25] J. Ohtani, T. Ooishi, T. Kawagoe, M. Niiro, M. Maruta, and H. Hidaka, “A sharable builtin
self-repair for multiple embedded memories,” in Proc. IEEE Conf. on Custom Integrated
Circuits, May 2001, pp. 187–190.
[26] M. Choi, N. Park, F. Lombardi, Y. B. Kim, and V. Piuri, “Optimal spare utilization in
repairable and reliable memory cores,” in Proc. IEEE Int’l Workshop on Memory Technology,
Design and Testing (MTDT), July 2003, pp. 64–71.
[27] M. Nicolaidis, N. Achouri, and S. Boutobza, “Optimal reconfiguration functions for column or
data-bit memory built-in self-repair,” in Proc. Conf. Design, Automation, and Test in Europe
(DATE), 2003, pp. 590–595.
[28] M. Nicolaidis, N. Achouri, and L. Anghel, “A memory built-in self-repair for high defect
densities based on error polarities,” in Proc. Int’l Symp. on Defect and Fault Tolerance in
VLSI Systems, Nov. 2003, pp. 459–466.
[29] A. Sehgal, A. Dubey, E. J. Marinissen, C. Wouters, H. Vranken, and K. Chakrabarty, “Yield
analysis for repairable embedded memories,” in Proc. IEEE European Test Workshop, May
2003, pp. 35–40.
[30] R. Zappa, C. Selva, D. R. andC. Torelli, M. Crestan, G. Mastrodomenico, and L. Albani, “Micro
programmable built-in self repair for SRAMs,” in Proc. IEEE Int’l Workshop on Memory
Technology, Design and Testing (MTDT), Aug. 2004, pp. 72–77.
[31] X. Du, S. M. Reddy, W.-T. Cheng, J. Rayhawk, and N. Mukherjee, “At-speed built-in selfrepair
analyzer for embedded word-oriented memories,” in Proc. Int’l Conf. on VLSI Design,
2004, pp. 895–900.
[32] S.-K. Lu and S.-C. Huang, “Built-in self-test and repair (bistr) techniques for embedded RAM,”
in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Aug.
2004, pp. 60–64.
[33] J.-Y. Fong, R. Acklin, J. Roscher, L. Feng, C. Laird, and C. Pietrzyk, “Nonvolatile repair
caches repair embedded SRAM abd new nonvolatile memories,” in Proc. Int’l Symp. on Defect
and Fault Tolerance in VLSI Systems, Oct. 2004, pp. 347–355.
[34] H.-Y. Lin, F.-M. Yeh, I.-Y. Chen, and S.-Y. Kuo, “An efficient perfect algorithm for memory
repair problems,” in Proc. Int’l Symp. on Defect and Fault Tolerance in VLSI Systems, Oct.
2004, pp. 306–313.
[35] S. K. Thakur, R. A. Parekhji, and A. N. Chandorkar, “On-chip test and repair of memories
for static and dynamic faults,” in Proc. Int’l Test Conf. (ITC), Oct. 2006, pp. 1–10.
[36] P. Ohler, S. Hellebrand, and H.-J.Wunderlich, “An integrated built-in test and repair approach
for memories with 2D redundancy,” in Proc. IEEE European Test Symp. (ETS), May 2007,
pp. 91–96.
[37] C.-L. Yang, Y.-C. Hsiao, and S.-K. Lu, “Efficient BISR techniques for embedded memories considering
cluster faults,” in Proc. Int’l Symp. on Pacific Rim Dependable Computing (PRDC),
Dec. 2007, pp. 224–231.
[38] S. Bahl, “A sharable built-in self-repair for semiconductor memories with 2-D redundancy
scheme,” in Proc. Int’l Symp. on Defect and Fault Tolerance in VLSI Systems, Sept. 2007, pp.
331–339.
[39] W. Jeong, I. Kang, K. Jin, and S. Kang, “A fast built-in redundancy analysis for memories
with optimal repair rate using line-based search tree,” IEEE Trans. on VLSI Systems, vol. 17,
no. 12, pp. 1665–1678, Dec. 2009.
[40] J. Chung, J. Park, and J. A. Abraham, “A built-repair analyzer with optimal repair rate for
word-oriented memories,” IEEE Trans. on VLSI Systems, vol. 21, no. 2, pp. 281–291, Feb.
2013.
[41] T.-J. Chen, J.-F. Li, and T.-W. Tseng, “Cost-efficient built-in redundancy analysis with optimal
repair rate for RAMs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits
and Systems, vol. 31, no. 6, pp. 930–940, Nov. 2012.
[42] T.-W. Tseng and J.-F. Li, “A low-cost built-in redundancy-analysis scheme for word-oriented
RAMs with 2-D redundancy,” IEEE Trans. on VLSI Systems, vol. 19, no. 11, pp. 1983–1995,
Nov. 2011.
[43] S.-K. Lu, Z.-Y. Wang, Y.-M. Tsai, and J.-L. Chen, “Efficient built-in self-repair techniques for
multiple repairable embedded RAMs,” IEEE Trans. on Computer-Aided Design of Integrated
Circuits and Systems, vol. 31, no. 4, pp. 620–629, Apr. 2012.
[44] B.-Y. Lin, M. Lee, and C.-W. Wu, “Exploration methodology for 3D memory redundancy
architectures under redundancy constraint,” in IEEE Asian Test Symp. (ATS), Nov. 2012,
pp. 1–6.
[45] Y.-J. Chang, Y.-J. Huang, and J.-F. Li, “A built-in redundancy-analysis scheme for RAMs with
3D redundancy,” in Proc. Int’l Symp. on VLSI Design, Automation, and Test (VLSI-DAT),
Apr. 2011, pp. 1–4.
[46] H.-N. Liu, Y.-J. Huang, and J.-F. Li, “A built-in self-repair method for RAMs in mesh-based
NoCs,” in Proc. Int’l Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2009,
pp. 259–262.
[47] C.-W. Chou, Y.-J. Huang, and J.-F. Li, “A built-in self-repair scheme for 3-D RAMs with interdie
redundancy,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems,
vol. 32, no. 4, pp. 572–583, Apr. 2013.
[48] R. Manikandan and R. Dhivyapriya, “Efficient built in selt repair techniques for repairing
multiport embedded RAMs,” in Proc. Int’l Conf. on Green Computing Communication and
Electrical Engineering (ICGCCEE), Mar. 2014, pp. 1–6.
[49] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in selfrepair
analyzer (CRESTA) for embedded DRAMs,” in Proc. Int’l Test Conf. (ITC), 2000, pp.
567–574.
[50] D. Xiaogang, S. M. Reddy, W.-T. Cheng, J. Rayhawk, and N. Mukherjee, “At-speed bulitin
self-repair analyzer for embedded word-oriented memories,” in Proc. Int’l Conf. on VLSI
Design, Oct. 2004, pp. 895–900.
[51] W. Jeong, J. Lee, T. Han, and S. Kang, “An advanced BIRA for memories with an optimal
repair rate and fast analysis speed by using a branch analysis,” IEEE Trans. on Computer-
Aided Design of Integrated Circuits and Systems, vol. 29, no. 12, pp. 2014–2026, Dec. 2010.
[52] J. Chung, J. Park, J. A. Abraham, E. Byun, and C.-J. Woo, “Reducing test time and area
overhead of an embedded memory array built-in repair analyzer with optimal repair rate,” in
Proc. IEEE VLSI Test Symp. (VTS), Apr. 2010, pp. 33–38.
[53] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in redundancy analysis for memory
yield improvement,” IEEE Trans. on Reliability, vol. 52, no. 4, pp. 386–399, Dec. 2003.
[54] S.-K. Lu, Y.-C. Tsai, C.-H. Hsu, K.-H. Wang, and C.-W. Wu, “Efficient built-in redundancy
analysis for embedded memories with 2-D redundancy,” IEEE Trans. on VLSI Systems, vol. 14,
no. 1, pp. 34–42, Jan. 2006.
[55] T.-W. Tseng, J.-F. Li, and D.-M. Chang, “A built-in redundancy-analysis scheme for RAM
with 2D redundancy using 1D local bitmap,” in Proc. Conf. Design, Automation, and Test in
Europe (DATE), Mar. 2006, pp. 53–58.
[56] D.-M. Chang, J.-F. Li, and Y.-J. Huang, “A built-in redundancy-analysis scheme for random
access memories with two-level redundancy,” Jour. of Electronic Testing: Theory and
Applications, vol. 24, no. 1, pp. 181–192, Jan. 2008.
[57] S. Takase and N. Kushiyama, “A 1.6-GByte/s DRAM with flexible mapping redundancy
technique and additional refresh scheme,” IEEE Jour. of Solid-State Circuits, vol. 34, no. 11,
pp. 1600–1606, 1999.
[58] T. Namekawa, S. Miyano, R. Fukuda, R. Haga, O. Wada, H. Banda, S. Takeda, K. Suda,
K. Mimoto, S. Yamaguchi, T. Ohkudo, H. Takato, and K. Numata, “Dynamically shiftswitched
dataline redundancy suitable for DRAM macro with wide data bus,” IEEE Jour.
of Solid-State Circuits, vol. 35, no. 5, pp. 705–712, 2000.
[59] Y.-W. Jeon, Y.-H. Jun, and S. Kim, “Column redundancy scheme for multiple I/O DRAM
using mapping table,” Electron. Lett., vol. 36, no. 11, pp. 940–942, 2000.
[60] G. Kitsukawa, M. Horiguchi, Y. Kawajiri, T. Kawahara, T. Akiba, Y. Kawase, T. Tachibana,
T. Sakai, M. Aoki, S. Shukuri, K. Sagara, R. Nagai, Y. Ohji, N. Hasegawa, N. Yokoyama,
T. Kisu, H. Yamashita, T. Kure, and T. Nishida, “256-Mb DRAM circuit technologies for file
applications,” IEEE Jour. of Solid-State Circuits, vol. 28, no. 11, pp. 1105–1113, 1993.
[61] S. Kuge, F. Morishita, T. Tsuruda, S. Tomishima, M. Tsukude, T. Yamagata, and K. Arimoto,
“SOI-DRAM circuit technologies for low power high speed multigiga scale memories,” IEEE
Jour. of Solid-State Circuits, vol. 31, no. 4, pp. 586–591, 1996.
[62] T. Kirihata, Y. Watanabe, H. Wong, J. K. DeBrosse, M. Yoshida, D. Kato, S. Fujii, M. R.
Wordeman, P. Poechmueller, S. A. Parke, and Y. Asao, “Fault-tolerant designs for 256 Mb
DRAM,” IEEE Jour. of Solid-State Circuits, vol. 31, no. 4, pp. 558–566, 1996.
[63] K. Furutani, T. Ooishi, M. Asakura, H. Hidaka, and H. Ozaki, “A board level parallel test
and short circuit failure repair circuit for high-density, low-power DRAMs,” in Symp. on VLSI
Circuits Digest of Technical Papers, Honolulu, 1996, pp. 70–71.
[64] J.-F. Li, R.-S. Tzeng, and C.-W. Wu, “Diagnostic data compression techniques for embedded
memories with built-in self-test,” Jour. of Electronic Testing: Theory and Applications, vol. 18,
no. 4-5, pp. 515–527, Aug.-Oct. 2002.
[65] A. Ohba, “A 7-ns 1-Mb BiCMOS ECL SRAM with shift redundancy,” IEEE Jour. of Solid-
State Circuits, vol. 26, no. 4, pp. 507–512, Apr. 1991.
[66] R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, “RAISIN: a tool for evaluating redundancy
analysis schemes in repairable embedded memories,” IEEE Design & Test of Computers,
vol. 24, no. 4, pp. 919–931, Aug.-Sep. 2007.
[67] C.-W. Wang, J.-R. Huang, Y.-F. Lin, K.-L. Cheng, C.-T. Huang, C.-W. Wu, and Y.-L. Lin,
“Test scheduling of BISTed memory cores for SOC,” in IEEE Asian Test Symp. (ATS), Nov.
2002, pp. 356–361.
[68] M. Miyazaki, T. Yoneda, and H. Fujiwara, “A memory grouping method for sharing memory
BIST logic,” in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASPDAC),
2006, pp. 671–676.
[69] T. Yoneda, Y. Fukuda, and H. Fujiwara, “Test scheduling for memory cores with built-in
self-repair,” in IEEE Asian Test Symp. (ATS), 2007, pp. 199–204.
[70] I. Kim, Y. Zorian, G. Komoriya, H. Pham, F. P. Higgins, and J. L. Lweandowski, “Built in
self repair for embedded high density SRAM,” in Proc. Int’l Test Conf. (ITC), Oct. 1998, pp.
1112–1119.
[71] R. C. Aitken, “A modular wrapper enabling high speed BIST and repair for small wide memories,”
in Proc. Int’l Test Conf. (ITC), Oct. 2004, pp. 997–1005.
[72] T.-W. Tseng, J.-F. Li, C.-C. Hsu, A. Pao, K. Chiu, and E. Chen, “A reconfigurable built-in
self-repair scheme for multiple repairable RAMs in SOCs,” in Proc. Int’l Test Conf. (ITC),
Oct. 2006, pp. 1–8.
[73] E. Larsson, J. Pouget, and Z. Peng, “Abort-on-fail based test scheduling,” Jour. of Electronic
Testing: Theory and Applications, vol. 21, no. 6, pp. 651–658, Dec. 2005.
[74] B. Wang, J. Yang, J. Cicalo, A. Ivanov, and Y. Zorian, “Reducing embedded SRAM test time
under redundancy constraints,” in Proc. IEEE VLSI Test Symp. (VTS), Napa Valley, Apr.
2004, pp. 237–242.
[75] Q. Xu, B. Wang, A. Ivanov, and F. Y. Young, “Testing scheduling for built-in self-tested
embedded SRAMs with data retention faults,” IET Proc. Comput. Digital Tech., vol. 1, no. 3,
pp. 256–264, May 2007.
[76] C.-S. Hou and J.-F. Li, “Test and repair scheduling for built-in self-repair RAMs in SoCs,” in
Proc. IEEE Int. Symp. Electron. Des., Test, Applicat. (DELTA), Jan. 2010, pp. 3–7.
[77] Y. Zorian and S. Shoukourian, “Embedded-memory test and repair: infrastructure IP for SoC
yield,” IEEE Design & Test of Computers, vol. 20, no. 3, pp. 58–66, May-June 2003.
[78] C.-L. Su, R.-F. Huang, and C.-W. Wu, “A processor-based built-in self-repair design for embedded
memories,” in IEEE Asian Test Symp. (ATS), Nov. 2003, pp. 366–371.
[79] T.-W. Tseng, C.-S. Hou, and J.-F. Li, “Automatic generation of built-in self-repair circuits in
SoCs for minimizing the test time and area cost,” in Proc. IEEE VLSI Test Symp. (VTS),
May 2010, pp. 21–26.
[80] K. N. Granapathy, A. D. Singh, and D. K. Pradhan, “Yield optimization in large RAMs with
hierarchical redundancy,” IEEE Jour. of Solid-State Circuits, vol. 26, no. 9, pp. 1259–1264,
Sept. 1991.
[81] A. J. van de Goor, “Using march tests to test SRAMs,” IEEE Design & Test of Computers,
vol. 10, no. 1, pp. 8–14, Mar. 1993.
[82] S.-K. Lu, C.-L. Yang, Y.-C. Hsiao, and C.-W. Wu, “Efficient BISR techniques for embedded
memories considering cluster faults,” IEEE Trans. on VLSI Systems, vol. 18, no. 2, pp. 184–
193, 2009.
[83] M. Koyanagi, T. Fukushima, and T. Tanaka, “High-desity through silicon vias for 3-D LSIs,”
Proc. of the IEEE, vol. 97, no. 1, pp. 49–59, Jan. 2009.
[84] M. Motoyoshi, “Through-silicon via (TSV),” Proc. of the IEEE, vol. 97, no. 1, pp. 43–48, Jan.
2009.
[85] V. F. Pavlidis and E. G. Friedman, “Interconnect-based design methodologies for threedimensional
integrated circuits,” Proc. of the IEEE, vol. 97, no. 1, pp. 123–140, Jan. 2009.
[86] T. Zhang, R. Micheloni, G. Zhang, Z. R. Huang, and J. J.-Q. Lu, “3-D data storage power
delivery, and RF/optical transceiver- case studies of 3-D integration from system design perspectives,”
Proc. of the IEEE, vol. 97, no. 1, pp. 161–174, Jan. 2009.
[87] Semiconductor Industry Association, “International technology roadmap for semiconductors
(ITRI), 2011 edition,” Hsinchu, Taiwan, 2011.
[88] M. J. Marinissen, “Challenges and emerging solutions in testing TSV-based 21
2D- and 3Dstacked
ICs,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), Mar. 2012, pp.
1277–1282.
[89] M.Miyazaki, T. Yoneda, and H. Fujiwara, “A memory grouping method for sharing memory
BIST logic,” in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASPDAC),
Mar. 2006, pp. 671–676.
[90] C.-W. Wang, J.-R. Huang, Y.-F. Lin, K.-L. Cheng, C.-T. Huang, C.-W. Wu, and Y.-L. Lin,
“Test scheduling of BISTed memory cores for SOC,” in Proc. 11th IEEE Asian Test Symp.
(ATS), Guam, Nov. 2002, pp. 356–361.
[91] C.-S. Hou, J.-F. Li, and T.-W. Tseng, “Memory built-in self-repair planning framework for
RAMs in SoCs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems,
vol. 30, no. 11, pp. 1731–1743, Nov. 2011.
指導教授 李進福(Jin-Fu Li) 審核日期 2014-12-4
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