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姓名 殷鼎欽(Din-chin Yin) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 二幂次電容區塊陣列排列的動態效能指標 相關論文 檔案 [Endnote RIS 格式]
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至系統瀏覽論文 ( 永不開放)
摘要(中) 佈局的自動化設計在類比電路上可以大幅的降低設計時的高錯誤率、高複雜度的佈局操作所花費的時間與繁瑣的任務和昂貴的設計成本。由於敏感的寄生電容效應、元件的不匹配、製程變動與梯度效應都將導致佈局結果可能是一個不好的佈局，也造成了產品的不準確性與良率的降低。多數類比電路像是類比數位/數位類比轉換器或濾波器等等，其性能都依賴於準確的電容比值。對於要求準確的電容比值大都會使用多顆單位電容並聯取代單一顆大電容並考慮繞線引起的寄生效應，以減少一些不匹配的影響。
現存有許多種指標去衡量一個電容陣列，有鑑於此本論文比較了多個指標，並且使其往一特定方向統合，縮減成績分非線性(INL)和有效位數(ENOB)兩個指標，使得使用者能更快速的利用這兩個指標去判斷不同擺放之間的優劣。
摘要(英) Automated layout design on analog circuits can significantly reduce the high error rate of the design, the time complexity of the layout of the high cost of operation and tedious task and expensive design costs. Due to the mismatch sensitive parasitic capacitance effects, components, process variation and gradient effect will lead to the layout result can be a bad layout, also caused inaccuracies and lower product yield. Most of analog circuits such as analog-digital / digital-to-analog converters or filters, etc., and its performance is dependent on accurate capacitance ratio. For most of the requirements of the exact capacitance ratio of the capacitor in parallel using multiple satellites units substituted single and considering a large parasitic capacitance caused by winding, in order to reduce some of the effects of the mismatch.
Now there are too many metric to judging a capacitor array, so we need to unified them into a more accurate indicator. Thus the user can more quickly determine the advantages and disadvantages between the different displays. To let users to assess whether the results meet their desired capacitance.
關鍵字(中) ★ 動態性能指標 關鍵字(英) 論文目次 目錄
摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 vii
Chapter 1. 緒論 1
1.1動機與背景 1
1.2論文組織 2
Chapter 2. 電容陣列區塊佈局概念 3
2.1電容 3
2.2電容的不匹配 6
2.3電容匹配的規則 7
2.4空間相關性..……………………………………………………………..…..9
2.5積分非線性(Integral Non-linearity, INL) 12
2.6有效位數(Effective number of bits, ENOB) 14
2.6.1訊號雜訊比(Signal-to-noise ratio, SNR)……...…………………….14
2.6.2有效位數(Effective number of bits, ENOB)…………….………….14
Chapter 3. 電容陣列的擺放 16
3.1共質心(Commom-Centroid) 16
3.2變異數(Variance)與比例標準差(Rstd) 18
3.3電容分散性與不匹配 20
3.3.1一維排列…………………………………………………………….20
3.3.2二維排列…………………………………………………………….23
Chapter 4 實驗結果與分析 25
4.1 四種電容連比的實現………………………………...……..……………..25
4.1.1 6-bit 電容連比……...…………………………...………………….26
4.1.2 9-bit 電容連比……...……………………………...……………….27
Chapter 5 結論 30
References 31
圖目錄
圖2.1 平行板電容器 3
圖2.2 邊緣電場側視圖 4
圖2.3 MIM電容.....................................................5
圖2.4 DoublePoly電容................................................5
圖2.5 一維空間相關性 10
圖2.6 二維空間相關性 10
圖2.7 二維空間相關性關係 11
圖2.8 微分非線性(DNL) 13
圖2.9 積分非線性(INL) 13
圖2.10 功率頻譜圖 15
圖3.1 共質心佈局減少梯度效應的影響 17
圖3.2 同心圓及對稱順序概念 18
圖3.3 一維電容比2:2排列 ...........................................20
圖3.4 排列(a)的相關係數矩陣 21
圖3.5 排列(b)的相關係數矩陣 21
圖3.6 排列(c)的相關係數矩陣 22
圖3.7 二維電容比4:26排列 23
圖3.8 相關係數與不匹配程度關係圖 24
圖4.1 電容連比四種擺放方式 26
圖4.2 電容連比三種擺放方式 28
表目錄
表3.1 共質心佈局的四種規則……………..……………………………………….17
表3.2 假設μ=100fF，σ=10fF去計算相關係數與不匹配程度…………….….23
表4.1 指數比例的模擬參數6-bit 27
表4.2 指數比例排列演算法的比較6-bit 27
表4.3指數比例的模擬參數9-bit 29
表4.4 指數比例排列演算法的比較9-bit 29
參考文獻 References
[1] P.-W. Luo, J.-E. Chen, C.L. Wey, L.-C. Cheng, J.-J. Chen, and W.-C. Wu, ”Impact
of capacitance correlation on yield enhancement of mixed-signal/Analog
integrated circuits,” IEEE Trans. on Computer-Aided Design of Integrated
Circuits and Systems, vol. 27, No. 11, pp. 2097-2101, November 2008.
[2]D. Sayed and M. Dessouky, “Automatic generation of common-centroid capacitor
arrays with arbitrary capacitor ratio,” in Proc. Des., Automation Test European
Conference, pp. 576–580, Mar. 2002.
[3]P.-W. Luo, J.-E. Chen, M.-Y. Huang, and C.L. Wey, “Design methodology for yield enhancement of switched-capacitor analog integrated circuits,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No. 1, pp.352-361, Jan. 2011.
[4] Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, and Soon-Jyh Chang,” Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, VOL. 31, NO. 12, DECEMBER 2012
[5] Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, and Soon-Jyh Chang,” Common-Centroid Capacitor Placement Considering Systematic and Random Mismatches in Analog Integrated Circuits,” IEEE Design Automation Conference , pp.528-533, 5-9 June 2011
[6]J.-E. Chen, P.-W. Luo, and C.L. Wey, “Yield evaluation of analog placement with
arbitrary capacitor ratio,” Proc. of International Symp. on Quality Electronic
Design, pp. 179-184, 2009.
[7]C.-C. Huang, J.-E. Chen, C.L. Wey, and P.-W. Luo,” Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs,” Transactions on Design Automation of Electronic Systems, to appear 2015.
[8] J.-E. Chen, P.-W. Luo, and C.L. Wey, “Placement optimization for yield Improvement of switched-capacitor analog integrated circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.29, No.2, pp.313 318, Feb. 2010.
[9]C.-C. Huang, J.-E. Chen, C.L. Wey, and P.-W. Luo,” Optimal Common-Centroid-Based Unit Capacitor Placements for Yield Enhancement of Switched-Capacitor Circuits,” Transactions on Design Automation of Electronic Systems, 19, 1, Article 7, Apr. 2013
[10] Mark Po-Hung Lin, Vincent Wei-Hao Hsiao, and Chun-Yu Lin,” Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC,” IEEE Design Automation Conference , June 2014
指導教授 陳竹一(Jwu-E Chen) 審核日期 2015-7-13 推文 plurk
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