| 摘要(英) |
In the current evolution of semiconductors, circuit size is getting smaller and smaller, so the change process will result in a mismatch on the element. If we take the mismatch of wire into consideration, the parasitic effects on the circuit become very complex. Then, the relevance between analog components and circuits will become a major difficulty of circuit design. Circuit design automation therefore becomes an integral part, which not only can enhance our understanding of the whole circuit, but also can be helpful to find the necessary information in complicated circuit. It speedups the operation to the point where the human brain can’t be and therefore reliable automated design can be an important key to our design efficiency.
For such problems, first of all we define a single series resistor element and square resistors. In its design, elements can enhance the degree of matching quality. And in the setting of such elements, we can use all of the layout space for wiring, so the spatial distribution of the degree of utilization is improved. But in one track routing method, resistance matching between interconnects is guaranteed. After that setting the reorder unit may further identify the appropriate routing rule under severe restrictions, thus making the area less without affecting the degree of matching and balanced. At the end, the completed GUI is a better tool for designers. After all, you can′t make bricks without straw.
|
| 參考文獻 |
【1】 M. Bai, C. Auth, and et al. A 65nm logic technology featuring 35nm gate length, enhanced channel strain, 8 cu interconnect layers, low-k ILD and 0.57um2 SRAM cell. In Proceedings of International Electron Devices Meeting (IEDM), 2004.
【2】 A. Hastings and R. A. Hastings, The Art of Analog Layout, Prentice Hall, 2000.
【3】 D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley and Sons, Inc. , 1997
【4】 Mark Burns and Gordon W. Roberts, “An Introduction to Mixed-Signal IC Test and Measurement” New York: Oxford, 2001. pp.403-419
【5】 M. M. Ozdal and R. F. Hentschke, "Exact route matching algorithms for analog and mixed signal integrated circuit," in Proc. International Conference on Computer-Aided Design, 2009, pp231-238
【6】 M. M. Ozdal and R. F. Wong, “An Algorithmic Study of Exact Route Matching for Integrated Circuits,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 30, no. 12, pp. 1842–1855, DEC. 2011.
【7】 H. Onodea and K. Tamaru, "A global routing algorithm for analog circuits using a resistor array model," Proc. IEEE Int. Conf.,May 1996 pp.667-670
【8】 C. J. Liu, Y. C. Lin and J. C. Rau, "The Grid-Based Two-Layer Routing Algorithm Suitable for Cell/IP-Based Circuit Design," to appear in Proc. IEEE Int. Conf. Electronics, Circuits and Systems, 2008.
【9】 H. W. Leong and C. L. Liu, “Discretionary channel routing”, IEE Proceedings-Circuits, Devices, and Systems, Vol.135, April 1988, pp. 45-57.
【10】 B. Razavi, “Design of Analog CMOS Integrated Circuits,” Mcgraw-Hill, 2001
【11】 王政傑, “ARBa : An Automatic Resistance-Balanced Routing for Series Resistor Arrays”, 中央大學電機工程學系論文, 2013
【12】 張宇翔, “Channel Sticks Routing for a Resistor-string Array”, 中央大學電 機工程學系論文, 2013
【13】 Laker User Guide and Tutorial, Nov. 2003.
【14】 Laker TCL Reference, Nov. 2003.
|
[Endnote RIS 格式]
[相關文章]
[文章引用]
[完整記錄]
[館藏目錄]
至系統瀏覽論文 ( 永不開放)
plurk
funp
live
udn
HD
myshare
netvibes
friend
youpush
delicious
baidu
Google bookmarks
del.icio.us
hemidemi
facebook
twitter
google
reddit