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姓名 奚國綱(Kuo-kang Hsi) 查詢紙本館藏 畢業系所 電機工程學系在職專班 論文名稱 一個寬頻鎖相迴路具有全域操作的高線性度壓控振盪器
(A Wide Band PLL with A High Linearity VCO in Full Range)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 近年來超大型積體電路蓬勃發展，電路的效能及速度也隨著製程技術的精進而提升，且目前的晶片皆趨向整合成單晶片系統(System-on-Chip)，所以在整合系統中各個子電路
區塊常會出現操作的時脈相位不同，導致輸出資料出現錯誤，因此需要鎖相迴路(PLL)
來減少相位偏差，使得整合系統中各個子電路的時脈相位一致，減低輸出資料的錯誤，
其中的關鍵在於降低鎖相迴路輸出訊號的抖動，可以藉由壓控振盪器(VCO)的高線性度與
降低Kvco來達成此目標，本論文將致力於高線性度壓控振盪器的探討。
本論文提出之寬頻鎖相迴路具有全域操作的高線性度壓控振盪器，從構想
如何實現高線性度壓控振盪器開始，進而理論推導驗證高線性度壓控振盪器
的特性式 f=Kvco•Vctrl+fmin 的正確性，其中的關鍵點在於壓控振盪器的偏壓電路，
它的輸入電壓Vctrl與輸出電流Ictrl的關係必須是線性的，為此本論文提出四種
符合線性要求的偏壓架構，分析其優劣好壞，從中挑選出的最佳偏壓架構，
經過設計模擬確認，具有全域操作、寬頻、寬壓的優良特點，並以此為基礎建構出
多頻段具有全域操作的高線性度壓控振盪器，最後實現本論文之鎖相迴路，可產生具有
低抖動之五個相位的頻率，達到輸出訊號低抖動的效果，且在不同製程和溫度變化下，
80MHz~160MHz 的頻率範圍皆能正確鎖定。
本論文以CIC CMOS 0.18um 1P6M 虛擬製程來實現，電路的工作電壓為1.8V，操作溫
度範圍為0℃ ~ 75℃，鎖相迴路的輸入參考頻率範圍為5MHz~10MHz，輸出頻率範圍鎖定
在80MHz~160MHz，鎖定時輸出時脈抖動量為19.2ps~18.1ps (pk-pk)。鎖定時間在
51.5us~49.1us，其消耗功率為 1.86mW~3.29mW。
摘要(英) In recent years the performance and speed of VLSI circuits grew up with
scale-down process, and now the chip changes to integrate SOC. There is often
phase error or clock skew which generate asynchronous phenomenon in
different sub-circuit blocks. The different phase of operate clock that
caused to output data error in integrate system. Hence, it needs Phase-Locked Loop
(PLL) for decreasing phase error that make the clock phase is corresponding
in order to decrease output data error in sub-circuit of integrate system.
The key point is to decrease the jitter of PLL output signal. The high linearity
of Voltage-controlled Oscillator(VCO) achieves the goal.
In this thesis, a wide band PLL with a high linearity voltage-controlled
oscillator(HLVCO) in full range is proposed. How to achieve a HLVCO ? A idea is
the beginning. Then validate the correctness of the HLVCO characteristics:
f=KvcoVctrl+fmin by theoretic derivation. The key point is the performance of
VCO bias circuit in the overall develop process. That is the relations of input
voltage Vctrl and output current Ictrl of VCO bias have to be linear. In this
thesis, four bias architectures achieving linear requirement are presented. First
choose a best one from analyzing their advantages and drawbacks. Then from the
process of design, simulation to validate the best one posses good features of
full range operation, wide band and wide voltage. In the basis a multi-band HLVCO
in full range operation is constructed. Finally a PLL is developed in this thesis.
It produces five low jitter output phases achieving the goal of low output jitter
mentioned previously. In the different process corners and temperatures the
frequency range of 80MHz~160MHz is locked correctly.
We use the CIC CMOS 0.18um 1P6M virtual process with supplying 1.8V voltage
in proposed PLL. The temperature range is 0℃ ~ 75℃. The reference input frequency
range is 5MHz~10MHz and the output frequency range is 80MHz~160MHz. The jitter
of output frequency is 19.2ps~18.1ps (pk-pk). The lock time is 51.5us~49.1us and
the power consumption is 1.86mW~3.29mW.
關鍵字(中) ★ 寬頻
★ 鎖相迴路
★ 全域
★ 線性度
★ 振盪器關鍵字(英) ★ Wide Band
★ PLL
★ Linearity
★ VCO
★ Full Range論文目次 摘要........................................................................i
Abstract...................................................................ii
誌謝......................................................................iii
目錄.......................................................................iv
圖目錄...................................................................viii
表目錄....................................................................xii
第一章 緒論.................................................................1
1.1 研究動機.........................................................1
1.2 實現構想.........................................................1
1.3 論文架構.........................................................2
第二章 鎖相迴路簡介.........................................................3
2.1 鎖相迴路架構介紹.................................................3
2.2 相頻偵測器(Phase Frequency Detector, PFD) .......................4
2.3 充電泵(Charge Pump, CP) .........................................7
2.4 迴路濾波器(Loop Filter, LF) ....................................11
2.5 壓控振盪器(Voltage Controlled Oscillator, VCO) .................13
2.6 除頻器(Frequency Divider, FD) ..................................19
第三章 鎖相迴路系統分析....................................................20
3.1 鎖相迴路的線性模型..............................................20
3.2 鎖相迴路的轉移函數分析..........................................21
3.3 迴路濾波器設計..................................................28
3.3.1 設計策略..................................................28
3.3.2 迴路濾波器結論............................................30
第四章 全域操作的線性壓控振盪器............................................31
4.1 構想............................................................31
4.2 線性壓控振盪器(Linear VCO, LVCO)之偏壓(VCO_Bias)設計............33
4.2.1 傳統壓控振盪器之偏壓設計..................................33
4.2.2 本論文提出的線性壓控振盪器之偏壓設計......................35
4.3 證明線性的電流控制振盪器(Current Controlled OSC., CCO)..........36
4.3.1 扼流延遲單元構成的環型振盪器..............................36
4.3.2 證明線性的電流控制振盪器(CCO).............................38
4.3.3 證明線性的壓控振盪器(LVCO)................................39
4.3.4 其他型的線性電流控制振盪器(CCO)...........................40
4.4 線性壓控振盪器之偏壓架構........................................42
4.4.1 第一型線性壓控振盪器偏壓架構..............................42
4.4.2 第二型線性壓控振盪器偏壓架構..............................43
4.4.3 第三型線性壓控振盪器偏壓架構..............................44
4.4.4 第四型線性壓控振盪器偏壓架構..............................45
4.5 多頻段(Multi-Band)壓控振盪器之架構..............................47
4.5.1 一般的多頻段壓控振盪器架構................................47
4.5.2 本論文提出的多頻段壓控振盪器架構..........................48
4.6 線性壓控振盪器(LVCO)的設計規格與模擬結果........................49
4.6.1 線性壓控振盪器的設計規格..................................50
4.6.2 線性壓控振盪器的模擬結果..................................51
第五章 設計實現與模擬結果..................................................54
5.1 線性壓控振盪器(Linear VCO, LVCO)................................54
5.1.1 線性壓控振盪器偏壓電路的實現..............................55
5.1.2 前級放大器的實現與模擬....................................56
5.1.3 修正的軌對軌運算放大器....................................58
5.1.4 環形振盪器的實現..........................................61
5.1.5 壓控振盪器的模擬結果......................................62
5.2 頻帶電路(Band)..................................................63
5.2.1 頻帶電路的實現............................................63
5.2.2 頻帶的切換機制............................................64
5.2.3 頻帶的模擬結果............................................66
5.2.4 不同頻段的追鎖速度........................................67
5.3 除頻器(FD)......................................................68
5.3.1 除頻器的實現..............................................68
5.3.2 除頻器的模擬結果..........................................69
5.4 相頻偵測器(PFD).................................................70
5.4.1 本論文提出的修正的相頻偵測器的實現........................70
5.4.2 四態相頻偵測器的實現......................................71
5.4.3 三態相頻偵測器的模擬結果..................................73
5.4.4 四態相頻偵測器的模擬結果..................................73
5.4.5 鎖定偵測器(Lock_Det)的實現................................74
5.4.6 鎖定偵測器的模擬結果......................................75
5.5 充電泵(CP)與迴路濾波器(LF)......................................76
5.5.1 充電泵的實現..............................................76
5.5.2 充電泵的模擬結果..........................................77
5.5.3 充電泵偏壓電路的實現......................................78
5.5.4 充電泵偏壓電路的模擬結果..................................79
5.5.5 迴路濾波器(LF)............................................80
5.6 死區的測量電路與模擬結果........................................81
5.6.1 死區的測量電路(BIAS+PFD+CP+LPF)...........................81
5.6.2 死區的模擬結果............................................82
5.7 PLL全電路模擬結果...............................................84
5.7.1 PLL輸出時脈Fout的眼圖:峰對峰抖動(週期抖動)的模擬結果......86
5.7.2 PLL回授時脈Ffb的眼圖:峰對峰抖動(週期抖動)與靜相差模擬結果.86
5.7.3 PLL鎖定80MHz 的模擬結果..................................87
5.7.4 PLL鎖定160MHz的模擬結果...................................89
5.7.5 PLL的前模擬整體特性......................................91
第六章 結論................................................................92
6.1 結論...........................................................92
6.2 未來的方向.....................................................93
參考文獻...................................................................94
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