具混亂時序注入機制之全數位高除數次諧波注入鎖定式鎖相迴路

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王威仁(Wei-ren Wang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具混亂時序注入機制之全數位高除數次諧波注入鎖定式鎖相迴路
(A High Division-Ratio All-Digital Sub-harmonically Injection-Locked PLL with Chaotic Injection Timing Technique)

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摘要(中)

本論文提出一個操作在5 GHz之低相位雜訊全數位次諧波注入鎖定式鎖相迴路。藉由一個額外之延遲鎖定迴路產生10個相位可用於次諧波注入之相位，此次諧波注入式鎖相迴路可以用較低的參考時脈但同時達到與高參考時脈之次諧波注入式鎖相迴路之低相位雜訊效果，同時利用一偽亂波產生器選擇注入相位，將注入之時序打亂，破壞其週期性，可以有效降低次諧波注入式鎖相迴路之高參考突波問題，透過選擇不同組合的注入相位順序，本架構提供了多種注入鎖定模式，可依照對需求之輸出訊號規格調整，達到不同的相位雜訊壓制量與參考突波量，同時由於使用了全數位式的架構，與傳統類比式鎖相迴路比較，其面積與功率消耗較少。
本論文之全數位式鎖相迴路使用90 nm CMOS製程實現晶片，其操作頻率為5 GHz，並且可在100 MHz參考頻率下擁有近於於1 GHz之次諧波注入鎖定之相位雜訊壓制效果，相位雜訊約為-99 dB。電路在操作電壓為1 V時，功率消耗為6.0 mW，而使用亂波注入的機制對於參考突波的衰減量約為14 dB。整體晶片面積為830 × 830 um2，核心電路的面積為228 × 161 um2。

摘要(英)

In this thesis, a 5 GHz low phase noise all-digital sub-harmonically injection-locked phase-locked loop (ADSILPLL) is proposed. An all-digital delay-locked loop (ADDLL) is added to provide extra 10 phases of low-phase-noise reference clock for the sub-harmonically injection operation. Proposed PLL uses the different sequence combination of those phases to achieve good phase noise performance without using high reference frequency. By adopting a pseudo chaotic code generator, the injected phase sequences can be randomized and break the periodicity of injection signal to solve the high reference spur issue at SILPLLs. By changing the injected phase sequence, this PLL also provides several different mode with different phase noise performance and reference spur performance for different specification requirement.
The experiment chip of the proposed ADPLL was implemented with 90 nm CMOS process. The measured output frequency is 5 GHz at 1.0 V supply voltage and power consumption is 6.0 mW. The phase noise is equal to -99 dB at 1 MHz frequency offset with 100 MHz reference frequency. The reference spur suppression is about 14 dB compared to full-speed injection. The full chip area is 830 × 830 um2 and the core area is 228 × 161 um2 .

關鍵字(中)

★ 鎖相迴路
★ 全數位式鎖相迴路
★ 注入鎖定式鎖相迴路
★ 參考突波
★ 高除率
★ 相位雜訊

關鍵字(英)

★ PLL
★ ADPLL
★ SILPLL
★ Reference spur
★ High division-ratio
★ Phase noise

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vii
表目錄 xi
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 3
第2章次諧波注入鎖定式鎖相迴路先前技術探討 5
2.1 鎖相迴路簡介 5
2.2 次諧波注入鎖定簡介 7
2.3 次諧波注入鎖定式鎖定迴路面臨到的問題與先前架構 12
2.3.1 注入時序問題 (Injection timing issue) 12
2.3.2 高除數時之相位雜訊壓制能力下降問題 17
2.3.3 注入造成的突波問題 19
2.4 預計論文規格 20
第3章具混亂時序注入機制之全數位高除數次諧波注入鎖定式鎖相迴路 21
3.1 電路架構與操作 21
3.1.1 全數位式鎖相迴路之操作 22
3.1.2 全數位式延遲鎖定迴路之操作 26
3.1.3 次諧波注入迴路之操作 27
3.2 鎖相迴路系統分析 32
3.2.1 全數位式鎖相迴路之S-domain分析 32
3.2.2 電荷幫浦鎖相迴路之S-domain分析 34
3.2.3 計算數位迴路濾波器之參數 35
3.3 行為模擬 38
3.4 次諧波注入振盪器之系統分析 41
第4章子電路架構與設計考量 51
4.1 全數位式鎖相迴路之子電路設計 51
4.1.1 相位頻率偵測器 51
4.1.2 時間對數位轉換器 53
4.1.3 數位迴路濾波器 58
4.1.4 數位控制振盪器 59
4.1.5 除頻器 62
4.2 全數位延遲鎖定迴路之子電路設計 63
4.2.1 數位控制延遲線 63
4.2.2 相位偵測器 65
4.2.3 上下數計數器 67
4.3 次諧波注入電路之子電路設計 68
4.3.1 脈波產生器 68
4.3.2 相位選擇器 70
4.3.3 注入模式選擇電路 72
第5章電路模擬與晶片量測結果 77
5.1 設計流程 77
5.2 布局後電路模擬 78
5.2.1 全數位式鎖相迴路 78
5.2.2 全數位式延遲鎖定迴路 79
5.2.3 次諧波注入鎖定效果 82
5.3 電路布局 86
5.4 晶片照相與量測環境設定 90
5.5 量測結果 95
5.5.1 全數位式鎖相迴路部分量測結果 95
5.5.2 全數位式延遲鎖定迴路部分量測結果 97
5.5.3 不同注入模式之次諧波注入鎖定效果量測 100
5.6 規格比較 106
第6章結論與未來研究方向 107
6.1 結論 107
6.2 未來研究方向 107
參考文獻 109

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指導教授

鄭國興(Kuo-hsing Cheng)

審核日期

2015-8-19

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