晶圓級封裝重佈線路製程光阻殘留之研究

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姓名

劉振坤(Chen-Kun Liu) 查詢紙本館藏

畢業系所

光電科學與工程學系

論文名稱

晶圓級封裝重佈線路製程光阻殘留之研究
(The Research of Photoresist Residue of Wafer Level Chip Scale Package Redistribution Layer Process)

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至系統瀏覽論文 ( 永不開放)

摘要(中)

近年來電子產品隨摩爾定律，電子產品的功能及執行速度不斷提升及走向輕薄設計，以目前智慧型手機為例，除單純的輕薄設計外，鏡頭的畫素要求也愈來愈高，故半導體封裝的尺寸要求愈來愈小，且執行速度要求愈來愈快的狀況下，封裝製程容易因線路設計愈來愈密集而導致缺陷容易發生，因此考慮到製程良率及產品成本的狀況下，進行製程缺陷改善是必然的方向。
本論文第二章及第三章，針對晶圓級封裝重佈線路曝光製程光阻殘留的問題，討論發生的理論機制。主要以重佈線路曝光製程的曝光強度、曝光照射時間、曝光方式及鈍化層粗糙度等方向，並利用田口分析法針找出最佳控制因子，解決光阻殘留問題。
本論文第四章，探討重佈線路曝光製程光阻殘留原因，來自於使用不當的曝光強度及曝光照射時間過長，造成晶粒與晶粒之間反射光源過強，影響重佈線路曝光製程光阻殘留比例，減少曝光過程中光罩與晶圓接觸距離，以及鈍化層粗糙度增加，避免光源因漫射而造成之反射光源，以上兩種條件皆可有效降低光阻殘留。應用田口分析法找出曝光UV照射強度4mw/cm2，曝光照射時間65sec及曝光時光罩與晶圓距離為0㎛可得到最佳化參數設計。

摘要(英)

In recent years , according to Moore’s law, the electronic related products have been promoted on function and execution speed concepts and trend to light and thin design. A case study of smart phone, it is not only light and thin design, but also high pixel. So semi-conductor under the package size getting smaller and execution speed become faster, package process become lead design closer to induce defect occurrence. Therefore, consider process yield and products cost, defect improvement is needed.
In this thesis second chapter and chapter third, focus on Wafer Level Chip Scale Package Redistribution layers exposure process photo resistance residue problems, discuss the theoretical mechanisms occurrence. Mainly by the RDL exposure intensity, exposure time, exposure method, passivation layer roughness and use Taguchi methods to find out the optimized conditions to solve PR residue problems.
The fourth chapter, discuss RDL exposure process photoresist residue problems occurs from unsuitable exposure intensity and long exposure time, induce high reflection light between chip and chip. Hence, impact RDL exposure process PR residue ratio. To reduce exposure distance between mask and wafer and rise passivation layer roughness, both conditions could avoid diffusion to induce reflection light effectively. Taguchi method result: exposure intensity 4mw/cm2, exposure time 65sec, soft contact is the optimized condition.

關鍵字(中)

★ 光阻殘留
★ 曝光強度
★ 照射時間
★ 曝光方式
★ 鈍化層粗糙度

關鍵字(英)

★ photoresist residue
★ exposure intensity
★ exposure time
★ exposure mode
★ passivation layer roughness

論文目次

摘要 v
Abstract vi
誌謝 vii
目錄 viii
圖目錄 xi
表目錄 xiv
第一章緒論 1
1.1 前言 1
1.2 研究動機 1
1.3 研究目的 3
1.4 文獻回顧 4
第二章原理及晶圓級封裝重佈線路製程簡介 5
2.1基本原理 5
2.1.1 Snell’s Law 5
2.1.2 反射率與電阻相關性[9] 6
2.2晶圓級封裝介紹 10
2.2.1 何謂晶圓級封裝[16][17] 10
2.2.2 晶圓級封裝流程 11
2.3 重佈線路製程介紹 16
2.3.1 前處理 (Pre-treatment) 16
2.3.2 電鍍光阻 (Electrical Deposition Photo Resistance) 16
2.3.3 軟烤製程 (Soft bake) 18
2.3.4 曝光製程 (Exposure) 19
2.3.5 顯影 (Develop) 21
2.3.6 硬烤 (Post bake) 22
2.3.7 蝕刻 (Etch) 22
2.3.8 去光阻 (Photoresist strip) 22
第三章實驗流程步驟與實驗儀器 23
3.1 實驗流程 23
3.2 實驗條件 26
3.2.1 曝光能量參數調整 26
3.2.2 曝光對位模式調整 28
3.2.3 鈍化層表面粗糙度調整 29
3.2.4 田口分析法 29
3.3 實驗儀器與分析儀器 43
機台種類 43
機台型號 43
曝光機 43
SUSS MA8 43
自動光學檢測 43
RUDOLPH Explorer NSX320 43
原子力顯微鏡 43
原力Wet Etcher S8 43
顯微鏡 43
Nikon-MM800 43
3.3.1 曝光機 (Aligner) 43
3.3.2 自動光學檢測 (Automated Optical Inspection, AOI) 44
3.3.3 原子力顯微鏡(Atomic Force Microscope, AFM)[26] 45
3.3.4 顯微鏡(Microscope) 45
第四章實驗結果與討論 46
4.1 曝光機曝光能量調整 46
4.2 曝光機對位模式調整 55
4.3 鈍化層表面粗糙度調整 58
4.4 田口分析法分析結果 60
第五章結論與未來展望 63
5.1 結論 63
5.2 未來展望 64
參考文獻 65

參考文獻

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指導教授

張榮森

審核日期

2016-8-2

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