| 摘要(英) |
In OFDM, IFFT and cyclic prefix to avoid the circular convolution aliasing are usually used to ensure the orthogonality for all subchannels, while FBMC only requires orthogonality with adjacent subchannels. In order to fully exploit channel bandwidth, modulations in the subchannels must adapt to the neighbor orthogonality constraint, so Offset Quadrature Amplitude Modulation (OQAM) is used for this purpose. Frequency selective filter is accomplished by using longer and spectrally well-shaped prototype filters, and because of frequency selective filter, the sidelobe levels are lower comparing to OFDM. Combination of filter banks and OQAM modulation result in no need for guard time or cyclic prefix like OFDM, leading to higher bandwidth efficiency. In general, this technique is called Filter Bank Multicarrier (FBMC) technique.
In FBMC system, the transmitter is called synthesis filter bank. We can get an intuitive algorithm, implemented by Inverse Discrete Fourier Transform. Then, the receiver is called analysis filter bank, implemented by using Discrete Fouier Transform. Filter banks consists of Polyphase Network (PPN) filter and FFT processor, we. Because the condition of the system speed demand is not fast, we choose the memory-based IFFT/FFT processor. Finally, PPN filter and IFFT/FFT processor are combined in transmitter and receiver.
This dissertation presents a reconfigurable homogeneous memory-based FFT processor architecture. Specifically, this thesis reinvestigates a radix-2 FFT algorithm and rearranges an alternative signal flow graph (SFG) from conventional SFGs. By developing the alternative SFG, this thesis proves that the altered permutation of input data can maintain the original functionality of FFT computation. Consequently, the alternative SFG is readily realized as the architecture of homogeneous parallel structure with multiple processing elements to increase throughput. However, the proposed design retains the advantage of a small area for the memory-based architecture, and achieves the goals of fast operation and ease of control. |
| 參考文獻 |
[1] D. Matiæ, “OFDM as a possible modulation technique for multimedia applications in the range of mm waves,” TUD-TVS, Oct. 1998J. Lowery, L. B. Du, and J. Armstrong, “Performance of optical OFDM in ultralong-haul WDM lightwave systems,” J. Lightw. Technol., vol. 25, no. 1, pp. 131–138, Jan. 2008.
[2] A.Peled and A. Ruiz, “Frequency domain data transmission using reduced computational complexity algorithms,” in Proc. IEEE International Conference on ICASSP, vol. 5, April, 1980, pp. 964-967.
[3] FBMC-Primer_06-2010. http://www.ict-phydyas.org
[4] Viholainen, A., Bellanger, M., and Huchard M. PHYDYAS project, deliverable D5.1: Prototype filter and structure optimization. http://www.ict-phydyas.org
[5] P. P. Vaidyanathan, Multirate Systems And Filter Banks. 1993, Prentice-Hall.
[6] Shin-Yo, Lin. 2011. Homogeneous Reconfigurable Memory-based FFT Processor for Wireless Communication Systems. Taoyuan: National Central Univeristy. Electrical engineering.
[7] R. Radhouane, P, Liu, C. Modin, “Minimizing the memory requirement for continuous flow FFT implementation:Continuous flow mixed mode FFT(CFMM-FFT),” Proc. IEEE Int. Symp. Circuits Syst., vol. 1, pp.116-119, 2000-May
[8] J. Nadal, C. A. Nour, A. Baghdadi, "Low-complexity pipelined architecture for FBMC/OQAM transmitter", IEEE Trans. Circuits Syst. II Express Briefs, vol. 63, no. 1, pp. 19-23, Jan. 2016.
[9] C.-L. Hung, S.-S. Long, M.-T. Shiue, "A low power and variable-length FFT processor design for flexible MIMO OFDM systems", Proc. IEEE Int. Symp. Circuits Syst., pp. 705-708, 2009-May.
[10] Yaun-En, Yu. 2016. “FBMC Transmission System Design and FPGA Evaluation of Polyphase Filter for 5G Mobile System”, Taoyuan: National Central Univeristy. Electrical engineering.
[11] B. G. Jo, M. H. Sunwoo, "New continuous-flow mixed-radix (CFMR) FFT processor using novel in-place strategy", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 52, no. 5, pp. 911-919, May 2005.
[12] J. A. Hidalgo, J. Lopez, F. Aruguello, E. L. Zapata, "Area-efficient architecture for fast Fourier transform", IEEE Trans. Circuits Syst. II. Analog Digit. Signal Process. vol. 46, no. 2, pp. 187-193, Feb. 1999. |
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